MC9S08GT60ACFDER Freescale Semiconductor, MC9S08GT60ACFDER Datasheet - Page 101
![IC MCU 60K FLASH 4K RAM 48-QFN](/photos/12/16/121676/mc9s08gt60acfber_sml.jpg)
MC9S08GT60ACFDER
Manufacturer Part Number
MC9S08GT60ACFDER
Description
IC MCU 60K FLASH 4K RAM 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08GT60ACFDER.pdf
(302 pages)
Specifications of MC9S08GT60ACFDER
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
S08GT
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
39
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
M68EVB908GB60E, M68DEMO908GB60E
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
MC9S08GT60ACFDERTR
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Freescale Semiconductor
PTGPE[7:0]
PTGD[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTGPE7
PTGD7
Port PTG Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port
G pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
Pullup Enable for Port G Bits — For port G pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled. For port G pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
0
0
7
7
PTGPE6
PTGD6
0
0
6
6
Figure 6-34. Pullup Enable for Port G (PTGPE)
Figure 6-33. Port PTG Data Register (PTGD)
Table 6-26. PTGPE Field Descriptions
Table 6-25. PTGD Field Descriptions
PTGPE5
PTGD5
MC9S08GB60A Data Sheet, Rev. 2
0
0
5
5
PTGPE4
PTGD4
0
0
4
4
Description
Description
PTGPE3
PTGD3
3
0
3
0
PTGPE2
PTGD2
0
0
2
2
Chapter 6 Parallel Input/Output
PTGPE1
PTGD1
0
0
1
1
PTGPE0
PTGD0
0
0
0
0
101
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