C8051F321-GMR Silicon Laboratories Inc, C8051F321-GMR Datasheet - Page 230
C8051F321-GMR
Manufacturer Part Number
C8051F321-GMR
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F32xr
Specifications of C8051F321-GMR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
I2C, SMBus, SPI, UART, USB
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
21
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F320DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel / 10 bit, 7 Channel
Package
28MLP
Device Core
8051
Family Name
C8051F321
Maximum Speed
25 MHz
Operating Supply Voltage
3.3 V
For Use With
336-1480 - DAUGHTER CARD TOOLSTCK C8051F321336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F321-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
- Current page: 230 of 250
- Download datasheet (2Mb)
C8051F320/1
20.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/
timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port
pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused
the capture.
230
Timer Overflow
PCA Counter/
W
P
M
1
6
n
PCA Module 0
PCA Module 1
PCA Module 2
PCA Module 3
PCA Module 4
(for n = 0 to 4)
PCA0CPMn
E
C
O
M
n
C
A
P
P
n
(CCF0)
(CCF1)
(CCF2)
(CCF3)
(CCF4)
C
A
P
N
n
M
A
T
n
O
G
T
n
W
P
M
n
E
C
C
F
n
C
F
C
R
PCA0CN
C
C
F
4
Figure 20.3. PCA Interrupt Block Diagram
C
C
F
3
C
C
F
2
C
C
F
1
C
C
F
0
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
C
D
L
I
W
D
T
E
PCA0MD
W
D
C
K
L
C
P
S
2
C
P
S
1
0
1
0
1
0
1
0
1
0
1
C
P
S
0
C
E
F
0
1
Rev. 1.4
EPCA0
0
1
EA
0
1
Interrupt
Priority
Decoder
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