R5F21134DFP#U0 Renesas Electronics America, R5F21134DFP#U0 Datasheet - Page 64
R5F21134DFP#U0
Manufacturer Part Number
R5F21134DFP#U0
Description
IC R8C MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/13r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21132FPU0.pdf
(33 pages)
3.R5F21132FPU0.pdf
(226 pages)
4.R5F21134DFPU0.pdf
(224 pages)
Specifications of R5F21134DFP#U0
Core Size
16-Bit
Program Memory Size
16KB (16K x 8)
Oscillator Type
Internal
Core Processor
R8C
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
No. Of I/o's
22
Eeprom Memory Size
4KB
Ram Memory Size
1024Byte
Cpu Speed
20MHz
No. Of Timers
16
Digital Ic Case
RoHS Compliant
Controller Family/series
R8C/13
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21134DFP#U0R5F21134DFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- R5F211A2SPU0 PDF datasheet
- R5F21132FPU0 PDF datasheet #2
- R5F21132FPU0 PDF datasheet #3
- R5F21134DFPU0 PDF datasheet #4
- Current page: 64 of 224
- Download datasheet (3Mb)
R8C/13 Group
Rev.1.20
REJ09B0111-0120
Figure 10.3 Interrupt Control Registers
I n t e r r u p t c o n t r o l r e g i s t e r
b 7
b7
Jan 27, 2006
NOTES:
1. Only "0" can be written to the IR bit. (Do not write "1").
2. To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register.
3. If the INTOPL bit in the INTEN register is set to “1” (both edges), set the POL bit to "0 " (selecting falling edge).
4. The IR bit may be set to “1” (interrupt requested) when the POL bit is rewritten. Refer to the paragraph 19.2.5
b 6
b6
“Changing Interrupt Factor”.
Refer to the paragraph 19.2.6 “Changing Interrupt Control Registers”.
b 5
b5
0
b 4
b4
b 3
b3
b 2
b2
page 53 of 205
b 1
b1
b 0
b0
B i t s y m b o l
B i t s y m b o l
( b 7 - b 6 )
(2)
( b 7 - b 4 )
I L V L 0
I L V L 1
I L V L 2
ILVL1
I L V L 2
ILVL0
P O L
( b 5 )
I R
IR
KUPIC
ADIC
CMP1IC
S0TIC, S1TIC
S0RIC, S1RIC
INT2IC
TXIC
TYIC
TZIC
INT1IC
INT3IC
TCIC
CMP0IC
Symbol
INT0IC
Symbol
I n t e r r u p t p r i o r i t y l e v e l
s e l e c t b i t
I n t e r r u p t r e q u e s t b i t
Interrupt priority level
select bit
I n t e r r u p t r e q u e s t b i t
P o l a r i t y s e l e c t b i t
R e s e r v e d b i t
Nothing is assigned.
When write, set to “0”. When read, its content is indeterminate.
N o t h i n g i s a s s i g n e d .
W h e n w r i t e , s e t t o “ 0 ” . W h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e .
Bit name
B i t n a m e
Address
005D
(3 , 4 )
16
004D
004E
0050
0051
0052
0055
0056
0057
0058
0059
005A
005B
005C
16
16
16
16
16
16
16
16
Address
16
16
16
16
16
b2 b1 b0
0 0 0 : L e v e l 0 ( i n t e r r u p t d i s a b l e d )
0 0 1 : L e v e l 1
0 1 0 : L e v e l 2
0 1 1 : L e v e l 3
1 0 0 : L e v e l 4
1 0 1 : L e v e l 5
1 1 0 : L e v e l 6
1 1 1 : L e v e l 7
, 0053
, 0054
0 : Interrupt not requested
1 : Interrupt requested
b2 b1 b0
0: Interrupt not requested
1: Interrupt requested
0 : S e l e c t s f a l l i n g e d g e
1 : S e l e c t s r i s i n g e d g e
M u s t a l w a y s b e s e t t o “ 0 ”
0 0 0 : L e v e l 0 ( i n t e r r u p t d i s a b l e d )
0 0 1 : L e v e l 1
0 1 0 : L e v e l 2
0 1 1 : L e v e l 3
1 0 0 : L e v e l 4
1 0 1 : L e v e l 5
1 1 0 : L e v e l 6
1 1 1 : L e v e l 7
XX00X000
After reset
16
16
F u n c t i o n
F u n c t i o n
2
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
After reset
10.1 Interrupt Overview
2
2
2
2
2
2
2
2
2
2
2
2
2
R W
R W
R W
R W
R W
R W
RW
R W
RW
RW
RW
RW
(1 )
(1 )
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