R5F21254SNFP#U0 Renesas Electronics America, R5F21254SNFP#U0 Datasheet - Page 22
![IC R8C MCU FLASH 16K 52LQFP](/photos/12/18/121838/r5f21254snfp_u0_sml.jpg)
R5F21254SNFP#U0
Manufacturer Part Number
R5F21254SNFP#U0
Description
IC R8C MCU FLASH 16K 52LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21246SDFPU0.pdf
(61 pages)
3.R5F21246SDFPU0.pdf
(527 pages)
Specifications of R5F21254SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 22 of 300
- Download datasheet (2Mb)
Rev.2.00 Oct 17, 2005
REJ09B0001-0200
1.1 Features of R8C/Tiny Series
Chapter 1 Overview
The R8C/Tiny Series of single-chip microcomputers was developed for embedded applications.
The R8C/Tiny Series supports instructions tailored for the C language, with frequently used instructions
implemented in one-byte op-code. It thus allows development of efficient programs with reduced memory
requirements when using either assembly language or C. Furthermore, some instructions can be executed
in a single clock cycle, enabling fast arithmetic processing.
The instruction set comprises 89 discrete instructions matched to the R8C’s many addressing modes. This
powerful instruction set provides support for register-register, register-memory, and memory-memory op-
erations, as well as arithmetic/logic operations using single-bit and 4-bit data.
Some R8C/Tiny Series models incorporate an on-chip multiplier, allowing for high-speed computation.
1.1.1 Features of R8C/Tiny Series
1.1.2 Speed Performance
Data registers:
Address registers: Two 16-bit registers
Base registers:
Instructions suited to C language (stack frame manipulation): ENTER, EXITD, etc.
Instructions that do not discriminate by register or memory area MOV, ADD, SUB, etc.
Powerful bit manipulation instructions: BNOT, BTST, BSET, etc.
4-bit transfer instructions: MOVLL, MOVHL, etc.
Frequently used 1-byte instructions: MOV, ADD, SUB, JMP, etc.
High-speed 1-cycle instructions: MOV, ADD, SUB, etc.
Minimum 1-cycle instructions: Of 89 instructions, 20 are 1-cycle instructions. (Approximately 75% of
instructions execute in five cycles or fewer.)
Register-register transfer
Register-memory transfer
Register-register addition/subtraction 2 cycles
8 bits x 8 bits register-register operation 4 cycles
16 bits x 16 bits register-register operation 5 cycles
16 bits / 8 bits register-register operation 18 cycles
32 bits / 16 bits register-register operation 25 cycles
Register configuration
Versatile instruction set
Fast instruction execution time
page 2 of 263
Four 16-bit registers (of which two can be used as 8-bit registers)
Two 16-bit registers
2 cycles
2 cycles
1.1 Features of R8C/Tiny Series
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