MC908GR16ACFAE Freescale Semiconductor, MC908GR16ACFAE Datasheet - Page 119

• Manufacturer Part Number: MC908GR16ACFAE
• Description: IC MCU 16K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR16ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 12-4
When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Freescale Semiconductor
1. X = Don’t care
2. I/O pin pulled up to V
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance
PTAPUE
Bit
X
1
0
shows the port A I/O logic.
DDRA
Bit
0
0
1
DD
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
by internal pullup device
PTA
X
Bit
X
X
(1)
Input, Hi-Z
Input, V
MC68HC908GR16A Data Sheet, Rev. 1.0
Table 12-2. Port A Pin Functions
RESET
Figure 12-4. Port A I/O Circuit
I/O Pin
Output
Mode
DD
(2)
(4)
Table 12-2
DDRAx
Accesses to DDRA
PTAx
DDRA7–DDRA0
DDRA7–DDRA0
DDRA7–DDRA0
Read/Write
summarizes the operation of the port A pins.
PTAPUEx
PTA7–PTA0
Read
Pin
Pin
Accesses to PTA
V
DD
INTERNAL
PULLUP
DEVICE
PTAx
PTA7–PTA0
PTA7–PTA0
PTA7–PTA0
Write
Port A
(3)
(3)
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