D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 715
D12321VF25V
Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of D12321VF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Smart Card Mode Register (SCMR) Settings: The SDIR bit is cleared to 0 if the IC card is of
the direct convention type, and set to 1 if of the inverse convention type.
The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the
inverse convention type.
The SMIF bit is set to 1 when the smart card interface is used.
Examples of register settings and the waveform of the start character are shown below for the two
types of IC card (direct convention and inverse convention).
• Direct convention (SDIR = SINV = O/E = 0)
• Inverse convention (SDIR = SINV = O/E = 1)
With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to
state A, and transfer is performed in LSB-first order. The start character data above is H'3B.
The parity bit is 1 since even parity is stipulated for the smart card.
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level
to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F.
The parity bit is 0, corresponding to state Z, since even parity is stipulated for the smart card.
With the chip, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For
parity bit inversion, the O/E bit in SMR should be set to odd parity mode (the same applies to
both transmission and reception).
(Z)
(Z)
Ds
Ds
A
A
D0
D7
Z
Z
D1
D6
Z
Z
D2
D5
A
A
D3
D4
A
Z
D4
D3
A
Z
D5
D2
Z
A
Rev.6.00 Sep. 27, 2007 Page 683 of 1268
D6
D1
A
A
Section 15 Smart Card Interface
D7
D0
A
A
Dp
Dp
Z
Z
(Z)
(Z)
REJ09B0220-0600
State
State
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