C8051F005-GQ Silicon Laboratories Inc, C8051F005-GQ Datasheet

IC 8051 MCU 32K FLASH 64TQFP

C8051F005-GQ

Manufacturer Part Number
C8051F005-GQ
Description
IC 8051 MCU 32K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F00xr
Datasheets

Specifications of C8051F005-GQ

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F005DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
2304Byte
Cpu Speed
25MHz
No. Of Timers
4
No. Of Pwm Channels
5
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1188 - DEV KIT FOR F005/006/007
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1187

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Part Number:
C8051F005-GQR
0
Analog Peripherals
12-Bit ADC
-
-
-
-
-
-
Two 12-Bit DACs
-
-
Two Comparators
-
-
Internal Voltage Reference
V
On-Chip JTAG Debug
-
-
-
-
Precision Mixed Signal
DD
±1 LSB INL; no missing codes
Programmable throughput up to 100 ksps
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
Voltage output
10 µsec settling time
16 programmable hysteresis values
Configurable to generate interrupts or reset
On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Fully compliant with IEEE 1149.1 specification
Monitor/Brown-out Detector
XTAL1
XTAL2
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
DGND
DGND
DGND
AGND
AGND
VREF
DAC1
DAC0
CP0+
CP1+
VDD
VDD
VDD
TMS
TDO
CP0-
CP1-
TCK
RST
AV+
AV+
TDI
CP0
Analog Power
Digital Power
VREF
M
A
U
X
Oscillator
Oscillator
External
JTAG
Monitor
Internal
CP1
Logic
Circuit
VDD
(12-Bit)
(12-Bit)
DAC1
DAC0
SENSOR
TEMP
Prog
Gain
Boundary Scan
Debug HW
WDT
25 MIPS, 32 kB Flash, 12-Bit ADC, 64-Pin Mixed-Signal MCU
100 ksps
System Clock
(12-Bit)
Copyright © 2004 by Silicon Laboratories
ADC
Reset
C
8
0
5
1
o
e
r
SFR Bus
256 Byte
2048 Byte
FLASH
32 kB
RAM
XRAM
High-Speed 8051 µC Core
-
-
-
Memory
-
-
Digital Peripherals
-
-
-
-
-
Clock Sources
-
-
-
Supply Voltage: 2.7 to 3.6 V
-
-
64-Pin TQFP
Temperature Range: –40 to +85 °C
Pipelined instruction architecture; executes 70% of Instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler; up to 21 interrupt sources
2304 bytes data RAM
32 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
32 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports
available concurrently
Programmable 16-bit counter/timer array with five capture/compare
modules
4 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Internal programmable oscillator: 2–16 MHz
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
Typical operating current: 12.5 mA at 25 MHz
Multiple power saving sleep and shutdown modes
SPI Bus
Timer 3
SMBus
Timers
5-Chnl
UART
Port 0
Port 1
Port 2
Port 3
Latch
Latch
Latch
Latch
0,1,2
PCA
C
R
O
B
A
R
W
C
H
S
S
S
T
I
C8051F005
P
0
D
P
1
D
P
2
D
P
3
D
r
v
r
v
r
v
r
v
6.15.2004
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

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C8051F005-GQ Summary of contents

Page 1

... FLASH 0 256 Byte Timer 3 5 Reset RAM Port 0 1 Latch 2048 Byte XRAM Port 1 Latch C Port 2 o Latch r SFR Bus e Port 3 Latch ADC (12-Bit) Copyright © 2004 by Silicon Laboratories C8051F005 P0 P0.1 0 P0.2 R P0.3 D P0 P0 P1 P1.2 P1.3 ...

Page 2

... SYSCLK = MCU system clock SYSCLK = MCU system clock 12 Guaranteed Monotonic 0 12 Specified from Data Word 014h to FEBh Guaranteed Monotonic Data Word = 014h To ½ LSB of full-scale 0 (each Comparator) | (CP+) – (CP 100 mV –0.25 –5 –10 C8051F005DK Development Kit MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 ...

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