M30625FGPGP#U5C Renesas Electronics America, M30625FGPGP#U5C Datasheet - Page 294
![IC M16C MCU FLASH 256K 128LQFP](/photos/12/21/122156/m30625fgpgp_u5c_sml.jpg)
M30625FGPGP#U5C
Manufacturer Part Number
M30625FGPGP#U5C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U5C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 22.5
Flash Memory Control Register 0
b7 b6 b5 b4
NOTES :
1.
2.
3.
4.
5.
6.
To set this bit to “1,” w rite “0” and then “1” in succession. Make sure no interrupts or DMA transfers w ill occur
before w riting “1” after w riting “0”.
Write to this bit w hen the NMI
than the flash memory.
Enter read array mode and set this bit to “0”.
To set this bit to “1,” w rite “0” and then “1” in succession w hen the FMR01 bit = 1. Make sure no interrupts or no
DMA transfers w ill occur before w riting “1” after w riting “0”.
Write to this bit from a program in other than the flash memory.
This flag is cleared to “0” by executing the Clear Status command.
Effective w hen the FMR01 bit = 1 (CPU rew rite mode). If the FMR01 bit = 0, although the FMR03 bit can be set to “1”
by w riting “1” in a program, the flash memory is neither placed in low pow er mode nor initialized.
This status includes w riting or reading w ith the Lock Bit Program or Read Lock Bit Status command.
Jan 10, 2006
0
b3 b2 b1 b0
FMR0 Register
Bit Symbol
Symbol
FMR00
FMR07
FMR01
FMR02
FMSTP
FMR05
FMR06
FMR0
(b4)
Page 277 of 390
—
____
RY/BY
CPU Rew rite Mode Select
Bit
Lock Bit Disable Select Bit
Flash Memory Stop Bit
Reserved Bit
User ROM Area Select Bit
(Effective in Only Boot Mode)
Program Status Flag
Erase Status Flag
pin is in the high state. Also, w hile in EW0 mode, w rite to this bit from a program in
(1)
___
Status Flag
Address
Bit Name
01B7h
(4)
(4)
(3, 5)
(2)
(3)
0 : Busy (being w ritten or erased)
1 : Ready
0 : Disables CPU rew rite mode
1 : Enables CPU rew rite mode
0 : Enables lock bit
1 : Disables lock bit
0 : Enables flash memory operation
1 : Stops flash memory operation
Set to “0”
0 : Boot ROM area is accessed
1 : User ROM area is accessed
0 : Terminated normally
1 : Terminated in error
0 : Terminated normally
1 : Terminated in error
(placed in low pow er mode, flash memory
initialized)
After Reset
00000001b
Function
22. Flash Memory Version
RW
RW
RW
RW
RW
RW
RO
RO
RO
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