M30626FHPFP#U5C Renesas Electronics America, M30626FHPFP#U5C Datasheet - Page 32
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M30626FHPFP#U5C
Manufacturer Part Number
M30626FHPFP#U5C
Description
IC M16C MCU FLASH 384K 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30626FHPFP#U5C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Package
100PQFP
Family Name
M16C
Maximum Speed
24 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
87
Interface Type
UART
On-chip Adc
26-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
11
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30626FHPFP#U5CM30626FHPFP#D3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ03B0001-0241
2.
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a
register bank. There are two register banks.
Figure 2.1
2.1
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are
the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data
register (R2R0). R3R1 is the same as R2R0.
Central Processing Unit (CPU)
Data Registers (R0, R1, R2 and R3)
b31
Jan 10, 2006
Central Processing Unit Register
NOTES:
1. These registers comprise a register bank. There are two register banks.
R2
R3
Page 30 of 96
b15
IPL
b19
b19
INTBH
b15
b15
b15
b15
R0H
R1H
b8
b7
U
PC
I
INTBL
b8 b7
USP
FLG
ISP
SB
R2
R3
A0
A1
FB
O
B
S
R0L
R1L
Z
D
C
b0
b0
b0
b0
b0
b0
2. Central Processing Unit (CPU)
Data Registers
Address Registers
Frame Base Registers
Interrupt Table Register
Program Counter
User Stack Pointer
Interrupt Stack Pointer
Static Base Register
Flag Register
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
(1)
(1)
(1)