MC9S12XEP100MAG Freescale Semiconductor, MC9S12XEP100MAG Datasheet - Page 393
MC9S12XEP100MAG
Manufacturer Part Number
MC9S12XEP100MAG
Description
IC MCU 16BIT 1M FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XEP100MAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
119
Number Of Timers
25
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
24-ch x 12-bit
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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ADDH
Operation
RD + IMM8:$00 ⇒ RD
Adds the content of high byte of register RD and a signed immediate 8 bit constant using binary addition
and stores the result in the high byte of the destination register RD. This instruction can be used after an
ADDL for a 16 bit immediate addition.
Example:
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
ADDH RD, #IMM8
N
∆
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RD[15]
Z
∆
ADDL
ADDH
old
old
V
∆
Source Form
& IMM8[7] & RD[15]
& IMM8[7] | RD[15]
C
∆
R2,#LOWBYTE
R2,#HIGHBYTE
old
new
& RD[15]
MC9S12XE-Family Reference Manual Rev. 1.23
| RD[15]
Add Immediate 8 bit Constant
Address
Mode
IMM8
new
; R2 = R2 + 16 bit immediate
old
& IMM8[7] & RD[15]
| IMM8[7] & RD[15]
(High Byte)
1
1
1
0
new
1
new
Machine Code
RD
Chapter 10 XGATE (S12XGATEV3)
IMM8
ADDH
Cycles
P
393
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