MC9S12DJ256CPVE Freescale Semiconductor, MC9S12DJ256CPVE Datasheet - Page 54

• Manufacturer Part Number: MC9S12DJ256CPVE
• Description: IC MCU 256K FLASH 4K EE 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12DJ256CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12D
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 8
• Operating Supply Voltage: - 0.3 V to + 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68KIT912DP256
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Function 1
MC9S12DT128B Device User Guide — V01.09
2.2 Signal Properties Summary
Table 2-1 summarizes the pin functionality. Signals shown in bold are not available in the 80 pin
package.
Pin Name
PAD[14:8]
VREGEN
PAD[15]
PAD[6:0]
RESET
PB[7:0]
PA[7:0]
EXTAL
PAD[7]
BKGD
TEST
XTAL
XFC
PE7
PE6
PE5
PE4
PE3
PE2
Function 2
ADDR[15:8]/
Pin Name
ADDR[7:0]/
DATA[15:8]
DATA[7:0]
AN1[6:0]
AN0[6:0]
NOACC
AN1[7]
IPIPE1
IPIPE0
LSTRB
AN0[7]
TAGHI
ECLK
R/W
—
—
—
—
—
—
Function 3
Pin Name
ETRIG1
ETRIG0
XCLKS
TAGLO
MODC
MODB
MODA
—
—
—
—
—
—
—
—
—
—
—
—
Freescale Semiconductor, Inc.
For More Information On This Product,
Function 4
Table 2-1 Signal Properties
Pin Name
Go to: www.freescale.com
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Function 5
Pin Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Powered
VDDPLL
VDDPLL
VDDPLL
VDDR
VDDR
VDDA
VDDA
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDX
VDDA
VDDA
N.A.
by
PUPBE
PUPEE
PUPEE
PUPEE
PUPEE
PUPAE
Always
PUCR/
PUCR/
PUCR/
PUCR/
PUCR/
PUCR/
While RESET pin
CTRL
None
None
None
None
None
None
NA
NA
NA
NA
Up
Internal Pull
Resistor
Down
low:
Disabled
Disabled
Reset
State
None
None
None
None
None
None
NA
NA
NA
NA
Up
Up
Up
Up
Up
Oscillator Pins
External Reset
Test Input
Voltage Regulator
Enable Input
PLL Loop Filter
Background Debug,
Tag High, Mode Input
Port AD Input,
Analog Inputs,
External Trigger
Input (ATD1)
Port AD Input,
Analog Inputs
(ATD1)
Port AD Input, Analog
Inputs, External
Trigger Input (ATD0)
Port AD Input, Analog
Inputs (ATD0)
Port A I/O,
Multiplexed
Address/Data
Port B I/O,
Multiplexed
Address/Data
Port E I/O, Access,
Clock Select
Port E I/O, Pipe
Status, Mode Input
Port E I/O, Pipe
Status, Mode Input
Port E I/O, Bus Clock
Output
Port E I/O, Byte
Strobe, Tag Low
Port E I/O, R/W in
expanded modes
Description