MC68332ACEH20 Freescale Semiconductor, MC68332ACEH20 Datasheet - Page 82

• Manufacturer Part Number: MC68332ACEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI, UART
• Minimum Operating Temperature: - 40 C
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SBK — Send Break
SCSR — SCI Status Register
TDRE — Transmit Data Register Empty Flag
TC — Transmit Complete Flag
RDRF — Receive Data Register Full Flag
RAF — Receiver Active Flag
82
MOTOROLA
RESET:
15
SBK provides the ability to transmit a break code from the SCI. If the SCI is transmitting when SBK is
set, it will transmit continuous frames of zeros after it completes the current frame, until SBK is cleared.
If SBK is toggled (one to zero in less than one frame interval), the transmitter sends only one or two
break frames before reverting to idle line or beginning to send data.
SCSR contains flags that show SCI operational conditions. These flags can be cleared either by hard-
ware or by a special acknowledgment sequence. The sequence consists of SCSR read with flags set,
followed by SCDR read (write in the case of TDRE and TC). A long-word read can consecutively access
both SCSR and SCDR. This action clears receive status flag bits that were set at the time of the read,
but does not clear TDRE or TC flags.
If an internal SCI signal for setting a status bit comes after the CPU has read the asserted status bits,
but before the CPU has written or read register SCDR, the newly set status bit is not cleared. SCSR
must be read again with the bit set. Also, SCDR must be written or read before the status bit is cleared.
Reading either byte of SCSR causes all 16 bits to be accessed. Any status bit already set in either byte
will be cleared on a subsequent read or write of register SCDR.
TDRE is set when the byte in register TDR is transferred to the transmit serial shifter. If TDRE is zero,
transfer has not occurred and a write to TDR will overwrite the previous value. New data is not trans-
mitted if TDR is written without first clearing TDRE.
TC is set when the transmitter finishes shifting out all data, queued preambles (mark/idle line), or
queued breaks (logic zero). The interrupt can be cleared by reading SCSR when TC is set and then by
writing the transmit data register (TDR) of SCDR.
RDRF is set when the content of the receive serial shifter is transferred to the RDR. If one or more errors
are detected in the received word, flag(s) NF, FE, and/or PF are set within the same clock cycle.
RAF indicates whether the SCI receiver is busy. It is set when the receiver detects a possible start bit
and is cleared when the chosen type of idle line is detected. RAF can be used to reduce collisions in
systems with multiple masters.
0 = Normal operation
1 = Break frame(s) transmitted after completion of current frame
0 = Register TDR still contains data to be sent to the transmit serial shifter.
1 = A new character can now be written to register TDR.
0 = SCI transmitter is busy
1 = SCI transmitter is idle
0 = Register RDR is empty or contains previously read data.
1 = Register RDR contains new data.
0 = SCI receiver is idle
1 = SCI receiver is busy
NOT USED
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
9
TDRE
8
1
TC
7
1
RDRF
6
0
RAF
5
0
IDLE
4
0
OR
3
0
NF
2
0
MC68332TS/D
FE
$YFFC0C
1
0
MC68332
PF
0
0