PIC16F526-I/P Microchip Technology, PIC16F526-I/P Datasheet - Page 25
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PIC16F526-I/P
Manufacturer Part Number
PIC16F526-I/P
Description
IC PIC MCU FLASH 1KX12 14DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F526-ISL.pdf
(122 pages)
2.PIC16F526-ISL.pdf
(22 pages)
3.PIC16F526-IP.pdf
(104 pages)
Specifications of PIC16F526-I/P
Program Memory Type
FLASH
Program Memory Size
1.5KB (1K x 12)
Package / Case
14-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
11
Ram Size
67 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 3x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
67 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 3 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162096 - HEADER MPLAB ICD2 PIC16F526 8/14
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
REGISTER 5-3:
5.4
Code protection does not prevent the CPU from
performing read or write operations on the Flash data
memory. Refer to the code protection chapter for more
information.
2010 Microchip Technology Inc.
bit 7
Legend:
S = Bit can only be set
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
Code Protection
Unimplemented: Read as ‘0’.
FREE: Flash Data Memory Row Erase Enable Bit
1 = Program memory row being pointed to by EEADR will be erased on the next write cycle. No write
0 = Perform write only
WRERR: Write Error Flag bit
1 = A write operation terminated prematurely (by device Reset)
0 = Write operation completed successfully
WREN: Write Enable bit
1 = Allows write cycle to Flash data memory
0 = Inhibits write cycle to Flash data memory
WR: Write Control bit
1 = Initiate a erase or write cycle
0 = Write/Erase cycle is complete
RD: Read Control bit
1 = Initiate a read of Flash data memory
0 = Do not read Flash data memory
U-0
—
will be performed. This bit is cleared at the completion of the erase operation.
EECON: FLASH CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
—
R/W-0
FREE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WRERR
R/W-0
WREN
R/W-0
x = Bit is unknown
PIC16F526
R/W-0
WR
DS41326E-page 25
R/W-0
RD
bit 0