ATMEGA168V-10AU Atmel, ATMEGA168V-10AU Datasheet - Page 98

IC AVR MCU 16K 10MHZ 32TQFP

ATMEGA168V-10AU

Manufacturer Part Number
ATMEGA168V-10AU
Description
IC AVR MCU 16K 10MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA168V-10AU

Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire, SPI, USART, Serial
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
23
Number Of Timers
3 bit
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
32TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
10 MHz
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
10MHz
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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14.8
98
Timer/Counter Timing Diagrams
ATmega48/88/168
• The timer starts counting from a value higher than the one in OCRnx, and for that reason
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set.
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 14-8. Timer/Counter Timing Diagram, no Prescaling
Figure 14-9
Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f
Figure 14-10
mode and PWM mode, where OCR0A is TOP.
symmetry around BOTTOM the OCnx value at MAX must correspond to the result of an up-
counting Compare Match.
misses the Compare Match and hence the OCnx change that would have happened on the
way up.
TCNTn
TCNTn
(clk
(clk
TOVn
TOVn
clk
clk
clk
clk
I/O
I/O
I/O
I/O
Tn
Tn
/1)
/8)
shows the same timing data, but with the prescaler enabled.
shows the setting of OCF0B in all modes and OCF0A in all modes except CTC
Figure 14-8
MAX - 1
MAX - 1
contains timing data for basic Timer/Counter operation. The figure
MAX
MAX
BOTTOM
BOTTOM
clk_I/O
/8)
T0
) is therefore shown as a
BOTTOM + 1
BOTTOM + 1
2545S–AVR–07/10

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