PIC24HJ32GP202-I/MM Microchip Technology, PIC24HJ32GP202-I/MM Datasheet - Page 47
![IC PIC MCU FLASH 32K 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC24HJ32GP202-I/MM
Manufacturer Part Number
PIC24HJ32GP202-I/MM
Description
IC PIC MCU FLASH 32K 28QFN
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP202-ISO.pdf
(272 pages)
3.PIC24HJ32GP202-ISO.pdf
(8 pages)
4.PIC24HJ32GP202-ISO.pdf
(12 pages)
5.PIC24HJ32GP204-IML.pdf
(244 pages)
Specifications of PIC24HJ32GP202-I/MM
Program Memory Type
FLASH
Program Memory Size
32KB (11K x 24)
Package / Case
28-QFN
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP202-ISO PDF datasheet #2
- PIC24HJ32GP202-ISO PDF datasheet #3
- PIC24HJ32GP202-ISO PDF datasheet #4
- PIC24HJ32GP204-IML PDF datasheet #5
- Current page: 47 of 244
- Download datasheet (4Mb)
4.4.1
Programmers can program one row of program Flash
memory at a time. To do this, it is necessary to erase
the 8-row erase page that contains the desired row.
The general process is:
1.
2.
3.
EXAMPLE 4-1:
© 2007 Microchip Technology Inc.
; Set up NVMCON for block erase operation
; Init pointer to row to be ERASED
Read
(512 instructions) and store in data RAM.
Update the program data in RAM with the
desired new data.
Erase the block (see Example 4-1):
a)
b)
c)
d)
e)
Set the NVMOP bits (NVMCON<3:0>) to
‘0010’ to configure for block erase. Set
ERASE (NVMCON<6>) and WREN (NVM-
CON<14>) bits.
Write the starting address of the page to be
erased into the TBLPAG and W registers.
Write 55h to NVMKEY.
Write AAh to NVMKEY.
Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the dura-
tion of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
MOV
MOV
MOV
MOV
MOV
TBLWTL W0, [W0]
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
eight
PIC24HJ32GP202/204 and PIC24HJ16GP304
#0x4042, W0
W0, NVMCON
#tblpage(PROG_ADDR), W0
W0, TBLPAG
#tbloffset(PROG_ADDR), W0
#5
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
rows
ERASING A PROGRAM MEMORY PAGE
of
program
memory
Preliminary
;
; Initialize NVMCON
;
; Initialize PM Page Boundary SFR
; Initialize in-page EA[15:0] pointer
; Set base address of erase block
; Block all interrupts with priority <7
; for next 5 instructions
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
4.
5.
6.
To protect against accidental operations, the write ini-
tiate sequence for NVMKEY must be used to allow any
erase or program operation to proceed. After the pro-
gramming command has been executed, the user
application must wait for the programming time until
programming is complete. The two instructions
following the start of the programming sequence
should be NOPs, as shown in Example 4-3.
Write the first 64 instructions from data RAM into
the program memory buffers (see Example 4-2).
Write the program block to Flash memory:
a)
b)
c)
d)
Repeat steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash mem-
ory.
Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
Write 55h to NVMKEY.
Write AAh to NVMKEY.
Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash mem-
ory is done, the WR bit is cleared
automatically.
DS70289A-page 45
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