PIC18F67J50-I/PT Microchip Technology, PIC18F67J50-I/PT Datasheet - Page 8

• Manufacturer Part Number: PIC18F67J50-I/PT
• Description: IC PIC MCU FLASH 64KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J50-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 49
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C/MSSP/SPI/EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J50 FAMILY
5. Module: Section 19.3 “SPI Mode” and
DS80481A-page 8
Note:
In Section 19.3 “SPI Mode” on page 231 and
Section 19.4 “I
following note is added to describe the procedure
to disable the MSSP module:
Disabling the MSSP module by clearing
the SSPEN bit (SSPxCON1<5>) may not
reset the module. It is recommended to
clear the SSPxSTAT, SSPxCON1 and
SSPxCON2 registers and select the mode
prior to setting the SSPEN bit to enable
the MSSP module.
Section 19.4 “I
2
C™ Mode” on page 241, the
2
C™ Mode”
6. Module: Figure 19-10: I
On page 252, the figure is replaced with the new
timing diagram provided in Figure 19-10.
Timing (Transmission, 7-Bit
Address)
© 2009 Microchip Technology Inc.
2
C™ Slave Mode