PIC18LF2455-I/SP Microchip Technology, PIC18LF2455-I/SP Datasheet - Page 143
![IC PIC MCU FLASH 12KX16 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF2455-I/SP
Manufacturer Part Number
PIC18LF2455-I/SP
Description
IC PIC MCU FLASH 12KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
7.PIC18LF4550-IML.pdf
(430 pages)
Specifications of PIC18LF2455-I/SP
Core Size
8-Bit
Program Memory Size
24KB (12K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
24
Eeprom Memory Size
256Byte
Ram Memory Size
2048Byte
Cpu Speed
48MHz
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2048 B
Interface Type
SPI, I2C, EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PCM18XR1 PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2455-ISO PDF datasheet #4
- PIC18F2455-ISO PDF datasheet #5
- PIC18F2455-ISO PDF datasheet #6
- PIC18LF4550-IML PDF datasheet #7
- Current page: 143 of 438
- Download datasheet (7Mb)
14.2
Timer3 can be configured for 16-bit reads and writes
(see Figure 14-2). When the RD16 control bit
(T3CON<7>) is set, the address for TMR3H is mapped
to a buffer register for the high byte of Timer3. A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, has
become invalid due to a rollover between reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
14.3
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Timer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increment on every rising edge of the oscillator source.
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.
TABLE 14-1:
© 2009 Microchip Technology Inc.
INTCON GIE/GIEH PEIE/GIEL
PIR2
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
Name
Timer3 16-Bit Read/Write Mode
Using the Timer1 Oscillator as the
Timer3 Clock Source
Timer3 Register Low Byte
Timer3 Register High Byte
OSCFIE
OSCFIP
OSCFIF
RD16
RD16
Bit 7
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
T3CCP2
T1RUN
CMIE
CMIP
CMIF
Bit 6
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS
T3CKPS1 T3CKPS0
TMR0IE
USBIF
USBIE
USBIP
Bit 5
PIC18F2455/2550/4455/4550
INT0IE
EEIE
EEIP
Bit 4
EEIF
T3CCP1
BCLIF
BCLIE
BCLIP
RBIE
Bit 3
14.4
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
14.5
If the CCP2 module is configured to generate a
(CCP2M3:CCP2M0 = 1011), this signal will reset
Timer3. It will also start an A/D conversion if the A/D
module is enabled (see Section 15.3.4 “Special
Event Trigger” for more information.).
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPR2H:CCPR2L register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from a CCP module, the write will
take precedence.
Special
Note:
T3SYNC TMR3CS
Timer3 Interrupt
Resetting Timer3 Using the CCP
Special Event Trigger
TMR0IF
HLVDIF
HLVDIE
HLVDIP
Bit 2
Event
The Special Event Triggers from the CCP2
module will not set the TMR3IF interrupt
flag bit (PIR2<1>).
Trigger
TMR3IF
TMR3IE
TMR3IP
INT0IF
Bit 1
in
TMR1ON
TMR3ON
CCP2IF
CCP2IE
CCP2IP
RBIF
Bit 0
DS39632E-page 141
Compare
on page
Values
Reset
56
56
56
55
55
54
55
53
mode
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