PIC16C64A-20/P Microchip Technology, PIC16C64A-20/P Datasheet - Page 96
![IC MCU OTP 2KX14 PWM 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC16C64A-20/P
Manufacturer Part Number
PIC16C64A-20/P
Description
IC MCU OTP 2KX14 PWM 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16LC62A-04SP.pdf
(337 pages)
4.PIC16C64A-04P.pdf
(8 pages)
Specifications of PIC16C64A-20/P
Program Memory Type
OTP
Program Memory Size
3.5KB (2K x 14)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
PIC16C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C/SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
33
Number Of Timers
3
Operating Supply Voltage
4 V to 6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
0 C
Controller Family/series
PIC16C
No. Of I/o's
33
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
3
Embedded Interface Type
I2C, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
444-1001 - DEMO BOARD FOR PICMICRO MCU
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C64A-20/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
PIC16C64A-20/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16LC62A-04SP PDF datasheet #3
- PIC16C64A-04P PDF datasheet #4
- Current page: 96 of 337
- Download datasheet (3Mb)
PIC16C6X
11.4.2
There are two address formats. The simplest is the
7-bit address format with a R/W bit (Figure 11-15). The
more complex is the 10-bit address with a R/W bit
(Figure 11-16). For 10-bit address format, two bytes
must be transmitted with the first five bits specifying this
to be a 10-bit address.
FIGURE 11-15: 7-BIT ADDRESS FORMAT
FIGURE 11-16: I
11.4.3
All data must be transmitted per byte, with no limit to the
number of bytes transmitted per data transfer. After
each byte, the slave-receiver generates an acknowl-
edge bit (ACK) (Figure 11-17). When a slave-receiver
doesn’t acknowledge the slave address or received
data, the master must abort the transfer. The slave
must leave SDA high so that the master can generate
the STOP condition (Figure 11-14).
FIGURE 11-18: DATA TRANSFER WAIT STATE
DS30234D-page 96
S
R/W
ACK
S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
ACK
S
R/W
- Start Condition
- Read/Write Pulse
- Acknowledge
SDA
SCL
ADDRESSING I
TRANSFER ACKNOWLEDGE
Start Condition
Acknowledge
Read/Write pulse
Condition
S
Start
S
MSb
2
C 10-BIT ADDRESS FORMAT
MSB
slave address
1
2
C DEVICES
Address
2
sent by slave
= 0 for write
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
acknowledgment
signal from receiver
LSb
R/W ACK
7
Sent by
Slave
R/W
8
ACK
9
byte complete
interrupt with receiver
Wait
State
FIGURE 11-17: SLAVE-RECEIVER
If the master is receiving the data (master-receiver), it
generates an acknowledge signal for each received
byte of data, except for the last byte. To signal the end
of data to the slave-transmitter, the master does not
generate an acknowledge (not acknowledge). The
slave then releases the SDA line so the master can
generate the STOP condition. The master can also
generate the STOP condition during the acknowledge
pulse for valid termination of data transfer.
If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line. This allows the slave to move the
received data or fetch the data it needs to transfer
before allowing the clock to start. This wait state tech-
nique can also be implemented at the bit level,
Figure 11-18. The slave will inherently stretch the clock,
when it is a transmitter, but will not when it is a receiver.
The slave will have to clear the SSPCON<4> bit to
enable clock stretching when it is a receiver.
Transmitter
Output by
Output by
SCL from
Receiver
clock line held low while
interrupts are serviced
Master
1
Data
Data
Condition
Data
Start
2
S
ACKNOWLEDGE
3 8
acknowledgment
signal from receiver
1
1997 Microchip Technology Inc.
ACK
2
not acknowledge
9
acknowledge
Condition
Stop
8
Acknowledgment
Clock Pulse for
P
9
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