PIC18LF4320-I/P Microchip Technology, PIC18LF4320-I/P Datasheet - Page 200
![IC MCU FLASH 4KX16 EEPROM 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18LF4320-I/P
Manufacturer Part Number
PIC18LF4320-I/P
Description
IC MCU FLASH 4KX16 EEPROM 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18F1320-ISS.pdf
(36 pages)
4.PIC18F2220-ISO.pdf
(394 pages)
5.PIC18F2220-ISO.pdf
(6 pages)
6.PIC18F2220-ISO.pdf
(6 pages)
7.PIC18F2220-ISO.pdf
(8 pages)
8.PIC18F2220-ISO.pdf
(6 pages)
9.PIC18F2220-ISO.pdf
(6 pages)
Specifications of PIC18LF4320-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, I2C, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
2 x 8 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
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Manufacturer
Quantity
Price
Company:
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Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
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Quantity:
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20 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18F1320-ISS PDF datasheet #3
- PIC18F2220-ISO PDF datasheet #4
- PIC18F2220-ISO PDF datasheet #5
- PIC18F2220-ISO PDF datasheet #6
- PIC18F2220-ISO PDF datasheet #7
- PIC18F2220-ISO PDF datasheet #8
- PIC18F2220-ISO PDF datasheet #9
- Current page: 200 of 394
- Download datasheet (7Mb)
PIC18F2220/2320/4220/4320
18.2
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free-running 8-bit timer. In
Asynchronous mode, bit BRGH (TXSTA<2>) also con-
trols the baud rate. In Synchronous mode, bit BRGH is
ignored. Table 18-1 shows the formula for computation
of the baud rate for different USART modes which only
apply in Master mode (internal clock).
Given the desired baud rate and F
integer value for the SPBRG register can be calculated
using the formula in Table 18-1. From this, the error in
baud rate can be determined.
Example 18-1 shows the calculation of the baud rate
error for the following conditions:
• F
• Desired Baud Rate = 9600
• BRGH = 0
• SYNC = 0
EXAMPLE 18-1:
TABLE 18-1:
TABLE 18-2:
DS39599G-page 198
0 (Asynchronous)
1 (Synchronous)
Legend: X = value in SPBRG (0 to 255)
TXSTA
RCSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
Desired Baud Rate
Solving for X:
Calculated Baud Rate = 16000000/(64 (25 + 1))
Error
Desired Baud Rate
Name
OSC
SYNC
= 16 MHz
USART Baud Rate Generator (BRG)
Baud Rate Generator Register
CSRC
SPEN
Bit 7
X
X
X
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
CALCULATING BAUD RATE ERROR
= F
= ((F
= ((16000000/9600)/64) – 1
= [25.042] = 25
= 9615
= (Calculated Baud Rate – Desired Baud Rate)
= (9615 – 9600)/9600
= 0.16%
Bit 6
RX9
TX9
OSC
OSC
Baud Rate = F
Baud Rate = F
/(64 (X + 1))
BRGH = 0 (Low Speed)
SREN
/Desired Baud Rate)/64) – 1
TXEN
Bit 5
OSC
, the nearest
SYNC
CREN
Bit 4
OSC
OSC
/(64 (X + 1))
/(4 (X + 1))
ADDEN
Bit 3
—
BRGH
FERR
Bit 2
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks, because the
F
error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
18.2.1
The system clock is used to generate the desired baud
rate; however, when a power-managed mode is
entered, the clock source may be operating at a differ-
ent frequency than in PRI_RUN mode. In Sleep mode,
no clocks are present and in PRI_IDLE, the primary
clock source continues to provide clocks to the baud
rate generator; however, in other power-managed
modes, the clock frequency will probably change. This
may require the value in SPBRG to be adjusted.
18.2.2
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
OSC
/(16 (X + 1)) equation can reduce the baud rate
OERR
TRMT
Bit 1
POWER-MANAGED MODE
OPERATION
SAMPLING
Baud Rate = F
RX9D
TX9D
Bit 0
BRGH = 1 (High Speed)
© 2007 Microchip Technology Inc.
0000 -010
0000 000x
0000 0000
POR, BOR
Value on
N/A
OSC
/(16 (X + 1))
0000 -010
0000 000x
0000 0000
Value on
all other
Resets
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