PIC18F448-I/P Microchip Technology, PIC18F448-I/P Datasheet
PIC18F448-I/P
Specifications of PIC18F448-I/P
Available stocks
Related parts for PIC18F448-I/P
PIC18F448-I/P Summary of contents
Page 1
... This document includes the programming specifica- tions for the following devices: • PIC18F242 • PIC18F248 • PIC18F252 • PIC18F258 • PIC18F442 • PIC18F448 • PIC18F452 • PIC18F458 2.0 PROGRAMMING OVERVIEW OF THE PIC18FXX2/XX8 The PIC18FXX2/XX8 can be programmed using the high voltage In-Circuit Serial Programming method, or the low voltage ICSP method. Both of these can be done with the device in the users’ ...
Page 2
... RB1 7 34 RB0 RD7 11 30 RD6 12 29 RD5 28 13 RD4 14 27 RC7 15 26 RC6 16 25 RC5 17 24 RC4 18 23 RD3 19 22 RD2 RC0 32 OSC2 31 PIC18F4X2 OSC1 30 PIC18F4X8 RE2 27 44L QFP RE1 26 RE0 25 RA5 24 23 RA4 2010 Microchip Technology Inc. ...
Page 3
... Read ‘0’s Read ‘0’s 2010 Microchip Technology Inc. PIC18FXX2/XX8 TABLE 2-2: IMPLEMENTATION OF CODE MEMORY Device PIC18F242 PIC18F248 PIC18F252 PIC18F258 PIC18F442 PIC18F448 PIC18F452 PIC18F458 Block Code Protection Address Controlled By: Range 000000h CPB, WRTB, EBTRB 0001FFh 000200h CP0, WRT0, EBTR0 001FFFh ...
Page 4
... ID Location 8 CONFIG1L CONFIG1H CONFIG2L CONFIG2H CONFIG3L CONFIG3H CONFIG4L CONFIG4H CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H Device ID1 Device ID2 2010 Microchip Technology Inc. TBLPTRL Addr[7:0] 200000h 200001h 200002h 200003h 200004h 200005h 200006h 200007h 300000h 300001h 300002h 300003h 300004h 300005h 300006h ...
Page 5
... I/Os in the high impedance state. FIGURE 2-4: ENTERING HIGH VOLTAGE PROGRAM/ VERIFY MODE P13 P12 D110 MCLR SDATA SCLK SDATA = Input 2010 Microchip Technology Inc. PIC18FXX2/XX8 FIGURE 2-5: accessed and FIGURE 2-6: MCLR PGM SDATA SCLK HIGH LEVEL PROGRAMMING FLOW ...
Page 6
... Data Payload SDATA = Input COMMANDS FOR PROGRAMMING 4-Bit Description Command 0000 0010 1000 1001 1010 1011 1100 1101 1110 1111 SAMPLE COMMAND SEQUENCE Data Core Instruction Payload 3C 40 Table Write, post-increment P5A Fetch Next 4-bit Command 2010 Microchip Technology Inc. ...
Page 7
... FIGURE 3-2: BULK ERASE TIMING SCLK SDATA 4-bit Command 16-bit Data Payload 2010 Microchip Technology Inc. TABLE 3-2: 4-Bit Command 0000 0000 0000 0000 0000 0000 1100 0000 Data 0000 80h 81h FIGURE 3-1: 83h 88h 89h 8Ah 8Bh 1 ...
Page 8
... Programming” command, and parameters P9 and P10 is shown in Figure 3-6. Note: The TBLPTR register must contain the same offset value when initiating the pro- gramming sequence as it did when the write buffers were loaded. 2010 Microchip Technology Inc. ...
Page 9
... Step 5: Repeat step 4, with Address Pointer incremented by 64 until all panels are erased. FIGURE 3-3: MULTI-PANEL SINGLE ROW ERASE CODE MEMORY FLOW Addr = Addr + 64 2010 Microchip Technology Inc. Core Instruction BSF EECON1, EEPGD BSF EECON1, CFGS BSF ...
Page 10
... Figure 3-4. The flowchart shown in Figure 3-5 depicts the logic necessary to completely write a PIC18FXX2/XX8 device. Note: The TBLPTR register must contain the same offset value when initiating the pro- gramming sequence as it did when the write buffers were loaded. 2010 Microchip Technology Inc. ...
Page 11
... Offset = TBLPTR<12:3> Panel 1 TBLPTR<21:13> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> Offset = TBLPTR<12:3> Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL. 2010 Microchip Technology Inc. PIC18FXX2/XX8 Erase Region (64 bytes) Offset = TBLPTR<12:6> Erase Region (64 bytes) Offset = TBLPTR<12:6> Erase Region (64 bytes) Offset = TBLPTR<12:6> Erase Region (64 bytes) Offset = TBLPTR< ...
Page 12
... MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and start programming NOP - hold SCLK high for time P9 2010 Microchip Technology Inc. ...
Page 13
... TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111 SCLK P5 SDATA 4-bit Command 2010 Microchip Technology Inc. Start LoopCount = 0 Configure Device for Multi-Panel Writes Panel Base Address = (N – 2000h Addr = Panel Base Address + (8 x LoopCount) Load 8 Bytes to Panel N Write Buffer at <Addr> All No ...
Page 14
... The erase will begin on the falling edge of the 4th SCLK after the WR bit is set. After the erase sequence terminates, SCLK must still be held low for the time specified by parameter P10 to allow high voltage discharge of the memory array. 2010 Microchip Technology Inc. ...
Page 15
... To continue writing data, repeat step 8, where the Address Pointer is incremented each iteration of the loop. 2010 Microchip Technology Inc. PIC18FXX2/XX8 Core Instruction BSF EECON1, EEPGD BSF EECON1, CFGS MOVLW 3Ch MOVWF TBLPTRU ...
Page 16
... Start Set Address Set Data Enable Write Unlock Sequence 55h - EECON2 AAh - EECON2 Start Write Sequence No WR bit clear? Yes No Done? Yes Done P10 16-bit Data Payload P5A Shift Out Data (see Figure 4-6) SDATA = Output 2010 Microchip Technology Inc. ...
Page 17
... Step 8: Disable writes. 0000 94 A6 Repeat steps 2 through 8 to write more data. Note 1: See Figure 4-4 for details on Shift Out Data timing. 2010 Microchip Technology Inc. PIC18FXX2/XX8 Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW < ...
Page 18
... MOVLW 00h MOVWF TBLPTRH MOVLW 00h MOVWF TBLPTRL Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and start programming NOP - hold SCLK high for time P9 2010 Microchip Technology Inc. ...
Page 19
... Address Program LSB Delay P9 Time for Write Done 2010 Microchip Technology Inc. PIC18FXX2/XX8 3.6 Configuration Bits Programming Unlike code memory, the configuration bits are pro- grammed a byte at a time. The “Table Write, Begin Pro- gramming” (4-bit command, ‘1111’) is used, but only 8 bits of the following 16-bit payload will be written ...
Page 20
... ID and configuration registers. Core Instruction MOVLW Addr[21:16] MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL TBLRD *+ P14 LSb Shift Data Out SDATA = Output P5A MSb Fetch Next 4-bit Command SDATA = Input 2010 Microchip Technology Inc. ...
Page 21
... All No code memory verified? Yes 2010 Microchip Technology Inc. PIC18FXX2/XX8 The Table Pointer must be manually set to 200000h (base address of the ID locations) once the code mem- ory has been verified. The post-increment feature of the Table Read 4-bit command may not be used to increment the Table Pointer beyond 1FFFFFh ...
Page 22
... BCF EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH BSF EECON1, RD MOVF EEDATA MOVWF TABLAT (1) Shift Out Data READ DATA EEPROM FLOW Start Set Address Read Byte Move to TABLAT Shift Out Data Done? Yes Done 2010 Microchip Technology Inc. ...
Page 23
... Checking” a device merely means to verify that all bytes read as FFh, except the configuration bits. Unused (reserved) configuration bits will read ‘0’ (pro- grammed). Refer to Table 5-2 for blank configuration expect data for the various PIC18FXX2/XX8 devices. 2010 Microchip Technology Inc. PIC18FXX2/XX8 ...
Page 24
... TABLE 5-1: DEVICE ID VALUE Device PIC18F242 PIC18F248 PIC18F252 PIC18F258 PIC18F442 PIC18F448 PIC18F452 PIC18F458 DS39576C-page 24 5.3 Low Voltage Programming (LVP) Bit The LVP bit in configuration register CONFIG4L enables low voltage ICSP programming. The LVP bit defaults to a ‘1’ from the factory. ...
Page 25
... CONFIG7L — — 30000Dh CONFIG7H — EBTRB 3FFFFEh DEVID1 DEV2 DEV1 3FFFFFh DEVID2 DEV10 DEV9 * This bit only applies to the PIC18FXX2 devices. 2010 Microchip Technology Inc. PIC18FXX2/XX8 Bit 5 Bit 4 Bit 3 Bit 2 — — — — OSCEN — — FOSC2 — ...
Page 26
... Background Debugger Enable bit 1 = Background debugger disabled 0 = Background debugger enabled Low Voltage Programming Enable bit 1 = Low voltage programming enabled 0 = Low voltage programming disabled Stack Overflow/Underflow Reset Enable bit 1 = Stack overflow/underflow will cause RESET 0 = Stack overflow/underflow will not cause RESET 2010 Microchip Technology Inc. ...
Page 27
... CONFIG6H WRTC CONFIG6H Note 1: This bit only applies to the PIC18FXX2 devices. 2: These bits only apply to the PIC18FX52/X58 devices. 2010 Microchip Technology Inc. PIC18FXX2/XX8 Description Code Protection bits (code memory area 0200h - 1FFFh Code memory not code protected 0 = Code memory code protected ...
Page 28
... An option to not include the configu- ration word information may be provided. When embedding configuration word information in the HEX file, it should start at address 300000h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. DS39576C-page 28 Description ...
Page 29
... Description Legend: Item CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Bytewise sum of lower four bits of all customer ID locations + = Addition & = Bitwise AND 2010 Microchip Technology Inc. PIC18FXX2/XX8 Checksum 0xAA at 0 Blank and Max Value Address C2B4 C20A C491 ...
Page 30
... Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Bytewise sum of lower four bits of all customer ID locations + = Addition & = Bitwise AND DS39576C-page 30 Checksum 2010 Microchip Technology Inc. 0xAA at 0 Blank and Max Value Address 82D8 822E 84B7 845D C2B4 C25A ...
Page 31
... PIC18F448 None SUM(0000:01FF)+SUM(0200:1FFF)+SUM(2000:3FFF)+(CFGW1L & 0000)+(CFGW1H & 0027)+(CFGW2L + 000F)+(CFGW2H & 000F)+(CFGW3L & 0000)+(CFGW3H & 0000)+(CFGW4L & ...
Page 32
... Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Bytewise sum of lower four bits of all customer ID locations + = Addition & = Bitwise AND DS39576C-page 32 Checksum 2010 Microchip Technology Inc. 0xAA at 0 Blank and Max Value Address 82D8 822E 84B7 845D C2B4 C25A ...
Page 33
... EEPROM information must be included. An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the HEX file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. 2010 Microchip Technology Inc. PIC18FXX2/XX8 ...
Page 34
... PP 10 — 2 — PP 2010 Microchip Technology Inc. Conditions Normal programming V Bulk erase operations 8 -3 meet AC specifications 5.0V DD 5.0V ...
Page 35
... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 36
... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 2010 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...