PIC24HJ256GP610-I/PT Microchip Technology, PIC24HJ256GP610-I/PT Datasheet - Page 114

• Manufacturer Part Number: PIC24HJ256GP610-I/PT
• Description: IC PIC MCU FLASH 128KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ256GP610-I/PT

• Core Size: 16-Bit
• Program Memory Size: 256KB (85.5K x 24)
• Core Processor: PIC
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b, 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC24
• No. Of I/o's: 85
• Ram Memory Size: 16KB
• Cpu Speed: 40MIPS
• No. Of Timers: 13
• No. Of Pwm Channels: 8
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 13
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 32 Channel)
• A/d Bit Size: 12 bit
• A/d Channels Available: 32
• Height: 1 mm
• Length: 12 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Width: 12 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24H
FIGURE 7-1:
7.1
Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)
contains the following registers:
• A 16-bit DMA Channel Control register
• A 16-bit DMA Channel IRQ Select register
• A 16-bit DMA RAM Primary Start Address register
• A 16-bit DMA RAM Secondary Start Address
• A 16-bit DMA Peripheral Address register
• A 10-bit DMA Transfer Count register (DMAxCNT)
An additional status register, DMACS, is common to all
DMAC channels. It contains the DMA RAM and SFR
write
respectively.
The
DMAxCNT are all conventional read/write registers.
Reads of DMAxSTA or DMAxSTB will read the con-
tents of the DMA RAM Address register. Writes to
DMAxSTA or DMAxSTB write to the registers. This
allows the user to determine the DMA buffer pointer
value (address) at any time.
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in
an IECx register in the interrupt controller, and the cor-
responding interrupt priority control bits (DMAxIP) are
located in an IPCx register in the interrupt controller.
DS70175C-page 112
(DMAxCON)
(DMAxREQ)
(DMAxSTA)
register (DMAxSTB)
(DMAxPAD)
Note: CPU and DMA address buses are not shown for clarity.
SRAM
DMAxCON,
collision
DMAC Registers
SRAM X-Bus
CPU
flags,
DMAxREQ,
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
XWCOLx
PORT 1
DMA RAM
CPU Peripheral DS Bus
Peripheral
Non-DMA
Ready
PORT 2
DMAxPAD
and
DMA DS Bus
PWCOLx,
and
Preliminary
DMA Controller
7.2
Each DMA channel has its own status and control reg-
ister (DMAxCON) that is used to configure the channel
to support the following operating modes:
• Word or byte size data transfers
• Peripheral to DMA RAM or DMA RAM to
• Post-increment or static DMA RAM address
• One-shot or continuous block transfers
• Auto-switch between two start addresses after
• Force a single DMA transfer (Manual mode)
Each DMA channel can be independently configured
to:
• Select from one of 19 DMA request sources
• Manually enable or disable the DMA channel
• Interrupt the CPU when the transfer is half or fully
DMA channel interrupts are routed to the interrupt con-
troller module and enabled through associated enable
flags.
The channel DMA RAM and peripheral write collision
Faults are combined into a single DMAC error trap
(Level 10) and are not maskable. Each channel has
DMA RAM write collision (XWCOLx) and peripheral
write collision (PWCOLx) status bits in the DMAC Sta-
tus register (DMACS) to allow the DMAC error trap
handler to determine the source of the Fault condition.
peripheral transfers
each transfer complete (Ping-Pong mode)
complete
Channels
DMA
Peripheral Indirect Address
DMAC Operating Modes
Peripheral 1
CPU
Ready
DMA
© 2006 Microchip Technology Inc.
DMA
Peripheral 3
CPU
Ready
DMA
DMA
Peripheral 2
CPU
Ready
DMA
DMA