EP9315-CB Cirrus Logic Inc, EP9315-CB Datasheet - Page 9

• Manufacturer Part Number: EP9315-CB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1261

ER638E2B
Workaround
Insure that this kind of sequence of instructions does not occur. Note that adding a small number of
intervening instructions may not be sufficient to avoid this problem. If such a sequence must occur, insure
that the first and third instructions are sufficiently far apart in the instruction stream by placing five other
instructions between them:
The five intervening instructions need not be nops and may appear before or after the second instruction.
Note that it is the instruction stream as executed by the processor, not the instructions as they appear in the
source code, which is relevant. Hence, cases where the program flow changes between the first and third
instruction must be considered.
To avoid this error when entering exception and interrupt handlers, the first five instructions of an exception
or interrupt handler should not be coprocessor instructions.
Description 3
Under certain circumstances, data in coprocessor general purpose registers or in memory may be
corrupted. The error appears as follows.
1) Let the first instruction be a serialized instruction that does not execute
2) Let the immediately following instruction be a two-word coprocessor load or store
In the case of a load, only the lower 32 bits (the first word) will be loaded into the target register. For example:
The lower 32 bits of c3 will correctly become what is at the memory address in r2, but the upper 32 bits of
c3 will not become what is at address r2 + 0x4.
In the case of a store, only the lower 32 bits (the first word) will be stored into memory. For example:
The lower 32 bits of c3 will be correctly written to the memory address in r2, but the upper 32 bits of c3 will
not be written.
cfadd32
nop
nop
cfsub32ne
nop
nop
nop
cfstr32
cfadd32ne
cfldr64
cfadd32ne
cfstr64
ized, at least one of the following must be true:
- The processor must be operating in serialized
- The instruction must move to or from the DSPSC (either cfmv32sc or cfmvsc32).
c0, c1, c2
c0, c3, c4
c0, [r2, #0x0]
c4, c5, c6
c3, [r2, #0x0]
c0, c1, c2
c3, [r2, #0x0]
(Continued)
; inserted extra instruction here
; inserted extra instruction here
; assume this does not execute
; inserted extra instruction here
; inserted extra instruction here
; inserted extra instruction here
; assume this does not execute
; assume this does not execute
2
mode.
1
. For an instruction to be serial-
4
.
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