Z8F0813SH005EC Zilog, Z8F0813SH005EC Datasheet - Page 165

• Manufacturer Part Number: Z8F0813SH005EC
• Description: IC Z8 ENCORE MCU FLASH 8K 20SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0813SH005EC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-3721

.
BITS
FIELD
RESET
R/W
PS025203-0405
OCD Status Register
DBGMODE
R/W
0
7
DBGMODE—Debug Mode
The device enters DEBUG mode when this bit is 1. When in DEBUG mode, the eZ8 CPU
stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is
automatically set when a BRK instruction is decoded and Breakpoints are enabled. If the
Flash Read Protect Option Bit is enabled, this bit can only be cleared by resetting the
device. It cannot be written to 0.
0 = The Z8 Encore!
1 = The Z8 Encore!
BRKEN—Breakpoint Enable
This bit controls the behavior of the
points are disabled and the
bit is 1, when a
automatically set to 1.
0 = Breakpoints are disabled.
1 = Breakpoints are enabled.
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a
Debug Acknowledge character (
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
Reserved—Must be 0.
RST—Reset
Setting this bit to 1 resets the Encore!
normal Power-On Reset sequence with the exception that the On-Chip Debugger is not
reset. This bit is automatically cleared to 0 at the end of reset.
0 = No effect.
1 = Reset the Flash Read Protect Option Bit device.
The OCD Status register reports status information about the current state of the debugger
and the system.
BRKEN
R/W
6
0
Table 93. OCD Control Register (OCDCTL)
BRK
DBGACK
®
®
instruction is decoded, the
R/W
Z8F0823 Series device is operating in NORMAL mode.
Z8F0823 Series device is in DEBUG mode.
5
0
BRK
P R E L I M I N A R Y
instruction behaves similar to an NOP instruction. If this
FFH
R
0
4
BRK
) to the host when a Breakpoint occurs.
®
Z8F0823 Series device. The device goes through a
instruction (opcode
R
DBGMODE
3
0
Reserved
Z8 Encore!
bit of the OCDCTL register is
R
0
2
00H
Product Specification
). By default, Break-
®
R
1
0
Z8F0823 Series
On-Chip Debugger
RST
R/W
0
0
148