C8051T601-GM Silicon Laboratories Inc, C8051T601-GM Datasheet - Page 29

• Manufacturer Part Number: C8051T601-GM
• Description: IC 8051 MCU 8K-EEPROM 11-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T60xr

Specifications of C8051T601-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 8
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-QFN
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051T600DK
• Minimum Operating Temperature: - 40 C
• For Use With: 336-1404 - KIT DEV FOR C8051T60X MCU'S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1652-5

Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
Dimension
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
(LMC) is calculated based on a Fabrication Allowance of 0.05mm.
mask and the metal pad is to be 60 m minimum, all the way around the pad.
to assure good solder paste release.
Small Body Components.
C1
C2
e
Table 7.2. QFN-10 PCB Land Pattern Dimensions
Figure 7.2. QFN-10 PCB Land Pattern
1.70
1.70
Min
0.50 BSC.
Max
1.80
1.80
Rev. 1.2
Dimension
C8051T600/1/2/3/4/5/6
X1
Y1
0.20
0.85
Min
Max
0.30
0.95
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