MC9S08SH4MTG Freescale Semiconductor, MC9S08SH4MTG Datasheet - Page 132
![IC MCU 8BIT 4K FLASH 16-TSSOP](/photos/12/25/122597/mc9s08sh4mtg_sml.jpg)
MC9S08SH4MTG
Manufacturer Part Number
MC9S08SH4MTG
Description
IC MCU 8BIT 4K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08SH4CTJ.pdf
(338 pages)
Specifications of MC9S08SH4MTG
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-TSSOP
Processor Series
S08SH
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
13
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08SH4MTG
Manufacturer:
Freescale
Quantity:
1 034
Part Number:
MC9S08SH4MTG
Manufacturer:
FREESCALE
Quantity:
20 000
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Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
132
ADLSMP
ADICLK
ADLPC
MODE
Field
ADIV
6:5
3:2
1:0
7
4
Reset:
W
R
Low Power Configuration — ADLPC controls the speed and power configuration of the successive
approximation converter. This is used to optimize power consumption when higher sample rates are not required.
0 High speed configuration
1 Low power configuration: {FC31}The power is reduced at the expense of maximum clock speed.
Clock Divide Select — ADIV select the divide ratio used by the ADC to generate the internal clock ADCK.
Table 9-6
Long Sample Time Configuration — ADLSMP selects between long and short sample time. This adjusts the
sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for
lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time
Conversion Mode Selection — MODE bits are used to select between 10- or 8-bit operation. See
Input Clock Select — ADICLK bits select the input clock source to generate the internal clock ADCK. See
Table
ADLPC
9-8.
7
0
shows the available clock configurations.
MODE
ADIV
00
01
10
11
00
01
10
11
0
6
Table 9-5. ADCCFG Register Field Descriptions
Figure 9-10. Configuration Register (ADCCFG)
ADIV
MC9S08SH8 MCU Series Data Sheet, Rev. 3
8-bit conversion (N=8)
Reserved
10-bit conversion (N=10)
Reserved
Table 9-6. Clock Divide Select
Table 9-7. Conversion Modes
0
5
Divide Ratio
1
2
4
8
ADLSMP
0
4
Mode Description
Description
0
3
MODE
Input clock ÷ 2
Input clock ÷ 4
Input clock ÷ 8
Clock Rate
Input clock
0
2
Freescale Semiconductor
0
1
ADICLK
Table
0
0
9-7.
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