C8051F557-IM Silicon Laboratories Inc, C8051F557-IM Datasheet - Page 173
C8051F557-IM
Manufacturer Part Number
C8051F557-IM
Description
IC 8051 MCU 16K FLASH 24-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F55xr
Specifications of C8051F557-IM
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
24-QFN
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
18
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 18x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
18
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F540DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1690-5
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C8051F55x/56x/57x
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings. When the WEAKPUD bit in XBR2 is 0, a weak pullup is enabled for all Port I/O config-
ured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is
turned off on an output that is driving a 0 to avoid unnecessary power dissipation.
Registers XBR0, XBR1, and XBR2 must be loaded with the appropriate values to select the digital I/O
functions required by the design. Setting the XBARE bit in XBR2 to 1 enables the Crossbar. Until the
Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn
Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority
Decode Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will deter-
mine the Port I/O pin-assignments based on the XBRn Register settings.
The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers
are disabled while the Crossbar is disabled.
Rev. 1.1
173
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