C8051F575-IM Silicon Laboratories Inc, C8051F575-IM Datasheet - Page 97

IC 8051 MCU 16K FLASH 40-QFN

C8051F575-IM

Manufacturer Part Number
C8051F575-IM
Description
IC 8051 MCU 16K FLASH 40-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F57xr
Datasheets

Specifications of C8051F575-IM

Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
40-QFN
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
33
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
33
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F560DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1716-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F575-IM
Manufacturer:
Silicon Labs
Quantity:
135
Part Number:
C8051F575-IMR
Manufacturer:
SILICON
Quantity:
290
C8051F55x/56x/57x
12.3. SFR Page Stack Example
The following is an example that shows the operation of the SFR Page Stack during interrupts. In this
example, the SFR Control register is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51
is executing in-line code that is writing values to SPI Data Register (SFR “SPI0DAT”, located at address
0xA3 on SFR Page 0x00). The device is also using the CAN peripheral (CAN0) and the Programmable
Counter Array (PCA0) peripheral to generate a PWM output. The PCA is timing a critical control function in
its interrupt service and so its associated ISR that is set to high priority. At this point, the SFR page is set to
access the SPI0DAT SFR (SFRPAGE = 0x00). See Figure 12.2.
SFR Page
Stack SFR's
0x0
SFRPAGE
(SPI0DAT)
SFRNEXT
SFRLAST
Figure 12.2. SFR Page Stack While Using SFR Page 0x0 To Access SPI0DAT
Rev. 1.1
97

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