C8051F504-IM Silicon Laboratories Inc, C8051F504-IM Datasheet - Page 167
![IC 8051 MCU 32K FLASH 48-QFN](/photos/12/27/122711/c8051f504-im_sml.jpg)
C8051F504-IM
Manufacturer Part Number
C8051F504-IM
Description
IC 8051 MCU 32K FLASH 48-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Specifications of C8051F504-IM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-QFN
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
32-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1527 - KIT DEV FOR C8051F50X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1519-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F504-IM
Manufacturer:
Silicon Labs
Quantity:
135
- Current page: 167 of 312
- Download datasheet (3Mb)
19.2. Programmable Internal Oscillator
All C8051F50x/F51x devices include a programmable internal high-frequency oscillator that defaults as the
system clock after a system reset. The internal oscillator period can be adjusted via the OSCICRS and
OSCIFIN registers defined in SFR Definition 19.3 and SFR Definition 19.4. On C8051F50x/F51x devices,
OSCICRS and OSCIFIN are factory calibrated to obtain a 24 MHz base frequency. Note that the system
clock may be derived from the programmed internal oscillator divided by 1, 2, 4, 8, 16, 32, 64, or 128, as
defined by the IFCN bits in register OSCICN. The divide value defaults to 128 following a reset.
19.2.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:
When one of the oscillator awakening events occur, the internal oscillator, CIP-51, and affected peripherals
resume normal operation, regardless of whether the event also causes an interrupt. The CPU resumes
execution at the instruction following the write to SUSPEND.
Note: When entering suspend mode, firmware must set the ZTCEN bit in REF0CN (SFR Definition 8.1).
Port 0 Match Event.
Port 1 Match Event.
Port 2 Match Event.
Port 3 Match Event.
Comparator 0 enabled and output is logic 0.
Rev. 1.2
C8051F50x/F51x
167
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