C8051F023-GQ Silicon Laboratories Inc, C8051F023-GQ Datasheet - Page 186
![IC 8051 MCU 64K FLASH 64TQFP](/photos/12/28/122847/c8051f023-gq_sml.jpg)
C8051F023-GQ
Manufacturer Part Number
C8051F023-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Specifications of C8051F023-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 10-bit
On-chip Dac
2-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1203
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F023-GQ
Manufacturer:
SiliconL
Quantity:
4 121
Company:
Part Number:
C8051F023-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F023-GQ
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
C8051F023-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F020/1/2/3
18.2.3. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the mas-
ter cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies
that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a “timeout” condi-
tion. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detect-
ing the timeout condition.
18.2.4. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus is desig-
nated as free. If an SMBus device is waiting to generate a Master START, the START will be generated following a
bus free timeout.
186
Rev. 1.4