MC9S12NE64VTUE Freescale Semiconductor, MC9S12NE64VTUE Datasheet - Page 138

• Manufacturer Part Number: MC9S12NE64VTUE
• Description: IC MCU 64K FLASH EEPROM 80-TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Processor Series: S12N
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 125 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12NE64E, DEMO9S12NE64E
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 70
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.625/3.465V
• Operating Supply Voltage (min): 2.357/2.375/3.135V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: TQFP
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 3 Port Integration Module (PIM9NE64V1)
If IIC takes precedence thePJ[7:6] pins become IIC open drain output pins.
During reset, pins PJ[7:6] are configured as inputs with pull-ups and pins PJ[3:0] are configured as
high-impedance inputs.
3.4.11
In all modes, port L pins PL[6:0] can be used either for general-purpose I/O or with the EPHY subsystem.
During reset, port L pins are configured as inputs with pull-ups.
3.4.12
All port and pin logic is located in the core module. Please refer to MEBI block description chapter for
details.
3.4.13
All ports start up as general-purpose inputs on reset.
3.4.14
3.4.14.1 Run Mode
No low power options exist for this module in run mode.
3.4.14.2 Wait Mode
No low power options exist for this module in wait mode.
3.4.14.3 Stop Mode
All clocks are stopped. There are asynchronous paths to generate interrupts from STOP on port G, H, and J.
3.5
The reset values of all registers are given in
3.5.1
All registers including the data registers get set/reset asynchronously.
properties after reset initialization.
138
Initialization/Application Information
Port L
Port A, B, E and BKGD Pin
External Pin Descriptions
Low Power Options
Reset Initialization
MC9S12NE64 Data Sheet, Rev. 1.1
Section 3.3, “Memory Map and Register
Table 3-5
summarizes the port
Freescale Semiconductor
Descriptions.”