M30620FCPGP#U7C Renesas Electronics America, M30620FCPGP#U7C Datasheet - Page 215
![IC M16C MCU FLASH 128K 100LQFP](/photos/12/29/122931/m30620fcpgp_u7c_sml.jpg)
M30620FCPGP#U7C
Manufacturer Part Number
M30620FCPGP#U7C
Description
IC M16C MCU FLASH 128K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30620FCPGP#U7C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Table 17.6
NOTES:
i=0 to 2
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
UCON
Register
1. The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long; bit 0 to bit 7
2. Set the bit 4 to bit 5 in the U0C1 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
3. TXD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to “0”.
when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.
included in the UCON register.
Jan 10, 2006
0 to 8
0 to 8
OER,FER,PER,SUM Error flag
0 to 7
SMD2 to SMD0
CKDIR
STPS
PRY, PRYE
IOPOL
CLK0, CLK1
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM
UiLCH
UiERE
0 to 7
0 to 7
0 to 7
0 to 7
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1
RCSP
7
Registers to Be Used and Settings in UART Mode
(2)
(2)
Bit
Page 198 of 390
Set transmission data
Reception data can be read
Set a bit rate
Set these bits to “100b” when transfer data is 7 bits long
Set these bits to “101b” when transfer data is 8 bits long
Set these bits to “110b” when transfer data is 9 bits long
Select the internal clock or external clock
Select the stop bit
Select whether parity is included and whether odd or even
Select the TXD/RXD input/output polarity
Select the count source for the UiBRG register
Select CTS or RTS to use
Transmit register empty flag
Enable or disable the CTS or RTS function
Select TXDi pin output mode
Set to “0”
LSB first or MSB first can be selected when transfer data is 8 bits long. Set this
bit to “0” when transfer data is 7 or 9 bits long.
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
Set this bit to “1” to use inverted data logic
Set to “0”
Set to “0”
Set to “0”
Set to “0”
Set to “0”
Select the source of UART0/UART1 transmit interrupt
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
Set this bit to “1” to accept as input CTS0 signal of UART0 from the P6_4 pin
Set to “0”
(1)
(1)
(3)
Function
17. Serial Interface
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