MC9S12HZ256CAL Freescale Semiconductor, MC9S12HZ256CAL Datasheet - Page 153
MC9S12HZ256CAL
Manufacturer Part Number
MC9S12HZ256CAL
Description
IC MCU 256K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12HZ128CAL.pdf
(692 pages)
Specifications of MC9S12HZ256CAL
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12H
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
85
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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4.3.7.2
Read: Anytime. Write: Never, writes to this register have no effect.
If the associated slew rate control is enabled (digital input buffer is disabled), a read returns a “1”. If the
associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the
associated pin.
4.3.7.3
Read: Anytime. Write: Anytime.
This register configures port pins PU[7:0] as either input or output.
When enabled, the SSD or MC modules force the I/O state to be an output for each associated pin and the
associated Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the
corresponding Data Direction Register bits revert to control the I/O direction of the associated pins.
Freescale Semiconductor
DDRU[7:0]
Reset
Reset
Field
7:0
W
W
R
R
DDRU7
PTIU7
Data Direction Port U
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Port U Input Register (PTIU)
Port U Data Direction Register (DDRU)
u
0
7
7
= Reserved or Unimplemented
DDRU6
PTIU6
u
0
6
6
Figure 4-45. Port U Data Direction Register (DDRU)
Figure 4-44. Port U Input Register (PTIU)
Table 4-32. DDRU Field Descriptions
DDRU5
PTIU5
MC9S12HZ256 Data Sheet, Rev. 2.05
u
0
5
5
DDRU4
PTIU4
u
0
4
4
Description
u = Unaffected by reset
DDRU3
PTIU3
u
0
3
3
Chapter 4 Port Integration Module (PIM9HZ256V2)
DDRU2
PTIU2
u
0
2
2
DDRU1
PTIU1
u
0
1
1
DDRU0
PTIU0
u
0
0
0
153
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