DF2189RVT20V Renesas Electronics America, DF2189RVT20V Datasheet
DF2189RVT20V
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DF2189RVT20V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8S/2189R Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be ...
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Rev. 2.00 Aug. 03, 2005 Page ii of xlii ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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This H8S/2189R Group is a series of microcomputers (MCUs) made up of the H8S/2000 CPU with Renesas Technology’s original architecture as its core, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, ...
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Bit order: Number notation: Signal notation: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ H8S/2189R Group manuals: Document Title H8S/2189R ...
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Rev. 2.00 Aug. 03, 2005 Page viii of xlii ...
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Main Revisions and Additions in this Edition Item Page All pages Appendix 759 C. Package Dimensions Figure C.1 Package Dimensions (TFP-144) Revisions (See Manual for Details) Suffix R is added to group name and product code. • H8S/2189 Group→ ...
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Rev. 2.00 Aug. 03, 2005 Page x of xlii ...
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Section 1 Overview................................................................................................1 1.1 Overview................................................................................................................................ 1 1.2 Internal Block Diagram.......................................................................................................... 2 1.3 Pin Description....................................................................................................................... 3 1.3.1 Pin Assignments ....................................................................................................... 3 1.3.2 Pin Assignment in Each Operating Mode................................................................. 4 1.3.3 Pin Functions .......................................................................................................... 10 Section 2 CPU......................................................................................................17 2.1 Features................................................................................................................................ 17 2.1.1 ...
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Program-Counter Relative—@(d:8, PC) or @(d:16, PC) ...................................... 48 2.7.8 Memory Indirect—@@aa:8 ................................................................................... 49 2.7.9 Effective Address Calculation ................................................................................ 50 2.8 Processing States.................................................................................................................. 52 2.9 Usage Notes ......................................................................................................................... 54 2.9.1 Note on TAS Instruction Usage.............................................................................. 54 2.9.2 Note on STM/LDM ...
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IRQ Status Registers (ISR16, ISR) ......................................................................... 86 5.3.5 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR, WUEMRB) ....................... 88 5.3.6 IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR) ..................................................................................................................... ...
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Port 2 Input Pull-Up MOS .................................................................................... 132 7.3 Port 3.................................................................................................................................. 133 7.3.1 Port 3 Data Direction Register (P3DDR).............................................................. 133 7.3.2 Port 3 Data Register (P3DR) ................................................................................ 134 7.3.3 Port 3 Pull-Up MOS Control Register (P3PCR)................................................... 134 7.3.4 Pin Functions ...
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Port A Output Data Register (PAODR) ................................................................ 165 7.10.3 Port A Input Data Register (PAPIN)..................................................................... 165 7.10.4 Pin Functions ........................................................................................................ 166 7.11 Port B ................................................................................................................................. 167 7.11.1 Port B Data Direction Register (PBDDR) ............................................................ 167 7.11.2 Port B Output ...
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Port F Input Pull-Up MOS.................................................................................... 191 7.16 Port G................................................................................................................................. 192 7.16.1 Port G Data Direction Register (PGDDR)............................................................ 192 7.16.2 Port G Output Data Register (PGODR)................................................................ 193 7.16.3 Port G Input Data Register (PGPIN) .................................................................... 193 7.16.4 Noise Canceller Enable ...
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Operation ........................................................................................................................... 228 9.6 Usage Notes ....................................................................................................................... 235 9.6.1 Module Stop Mode Setting ................................................................................... 235 Section 10 16-Bit Free-Running Timer (FRT) ..................................................237 10.1 Features.............................................................................................................................. 237 10.2 Input/Output Pins ............................................................................................................... 239 10.3 Register Descriptions ......................................................................................................... 239 10.3.1 Free-Running Counter (FRC) ...
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Section 11 16-Bit Timer Pulse Unit (TPU) ....................................................... 267 11.1 Features.............................................................................................................................. 267 11.2 Input/Output Pins............................................................................................................... 271 11.3 Register Descriptions......................................................................................................... 272 11.3.1 Timer Control Register (TCR).............................................................................. 273 11.3.2 Timer Mode Register (TMDR)............................................................................. 277 11.3.3 Timer I/O Control Register (TIOR)...................................................................... 279 11.3.4 ...
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Conflict between TCNT Write and Overflow/Underflow .................................... 336 11.8.12 Multiplexing of I/O Pins ....................................................................................... 337 11.8.13 Module Stop Mode Setting ................................................................................... 337 Section 12 8-Bit Timer (TMR) ..........................................................................339 12.1 Features.............................................................................................................................. 339 12.2 Input/Output Pins ............................................................................................................... 343 12.3 Register Descriptions ...
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Conflict between Compare-Matches A and B ...................................................... 371 12.9.5 Switching of Internal Clocks and TCNT Operation ............................................. 371 12.9.6 Mode Setting with Cascaded Connection ............................................................. 373 12.9.7 Module Stop Mode Setting ................................................................................... 373 Section 13 Watchdog Timer (WDT) ................................................................. ...
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Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ..................................................................................................................... 417 14.4.3 Clock..................................................................................................................... 418 14.4.4 SCI Initialization (Asynchronous Mode) .............................................................. 419 14.4.5 Serial Data Transmission (Asynchronous Mode) ................................................. 420 14.4.6 Serial Data Reception (Asynchronous Mode)....................................................... 422 14.5 Multiprocessor ...
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Section Bus Interface (IIC)..................................................................... 465 15.1 Features.............................................................................................................................. 465 15.2 Input/Output Pins............................................................................................................... 469 15.3 Register Descriptions......................................................................................................... 470 2 15.3 Bus Data Register (ICDR) .............................................................................. 470 15.3.2 Slave Address Register (SAR).............................................................................. 471 15.3.3 Second Slave Address ...
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A/D Conversion Accuracy Definitions .............................................................................. 550 16.7 Usage Notes ....................................................................................................................... 552 16.7.1 Permissible Signal Source Impedance .................................................................. 552 16.7.2 Influences on Absolute Accuracy ......................................................................... 552 16.7.3 Setting Range of Analog Power Supply and Other Pins ....................................... 553 16.7.4 Notes ...
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Duty Correction Circuit ..................................................................................................... 654 19.3 Medium-Speed Clock Divider ........................................................................................... 654 19.4 Bus Master Clock Select Circuit........................................................................................ 654 19.5 Subclock Input Circuit ....................................................................................................... 655 19.6 Subclock Waveform Forming Circuit................................................................................ 656 19.7 Clock Select Circuit ........................................................................................................... 656 19.8 Handling of ...
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Section 22 Electrical Characteristics .................................................................733 22.1 Absolute Maximum Ratings .............................................................................................. 733 22.2 DC Characteristics ............................................................................................................. 734 22.3 AC Characteristics ............................................................................................................. 740 22.3.1 Clock Timing ........................................................................................................ 741 22.3.2 Control Signal Timing .......................................................................................... 743 22.3.3 Timing of On-Chip Peripheral Modules ............................................................... 744 ...
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Rev. 2.00 Aug. 03, 2005 Page xxvi of xlii ...
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Section 1 Overview Figure 1.1 H8S/2189R Group Internal Block Diagram .................................................................. 2 Figure 1.2 H8S/2189R Group Pin Assignments (TFP-144) ........................................................... 3 Figure 1.3 Sample Design of Reset Signals with no Affection Each Other.................................. 16 Section 2 CPU Figure 2.1 Exception ...
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Figure 5.5 Block Diagram of Interrupts KIN15 to KIN0 and WUE15 to WUE0 (Example of WUE15 to WUE8).................................................................................. 96 Figure 5.6 Block Diagram of Interrupt Control Operation ......................................................... 106 Figure 5.7 Flowchart of Procedure up to Interrupt Acceptance in Interrupt ...
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Figure 10.13 Timing of Overflow Flag (OVF) Setting............................................................... 256 Figure 10.14 OCRA Automatic Addition Timing ...................................................................... 257 Figure 10.15 Timing of Input Capture Mask Signal Setting....................................................... 258 Figure 10.16 Timing of Input Capture Mask Signal Clearing .................................................... 258 Figure 10.17 ...
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Figure 11.30 Count Timing in Internal Clock Operation............................................................ 321 Figure 11.31 Count Timing in External Clock Operation .......................................................... 321 Figure 11.32 Output Compare Output Timing ........................................................................... 322 Figure 11.33 Input Capture Input Signal Timing........................................................................ 323 Figure 11.34 Counter Clear Timing ...
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Section 13 Watchdog Timer (WDT) Figure 13.1 Block Diagram of WDT .......................................................................................... 376 Figure 13.2 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 382 Figure 13.3 Interval Timer Mode Operation............................................................................... 383 Figure 13.4 OVF Flag Set Timing .............................................................................................. 383 Figure 13.5 ...
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Figure 14.23 Direct Convention (SDIR = SINV = O ...................................................... 442 Figure 14.24 Inverse Convention (SDIR = SINV = O .................................................... 443 Figure 14.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency ...
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Figure 15.15 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1)............................................................................ 509 Figure 15.16 Example of Stop Condition Issuance Timing in Master Receive Mode (MLS = ACKB = 0, WAIT = 1)............................................................................ 509 Figure ...
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Section 18 Flash Memory (0.18-µm F-ZTAT Version) Figure 18.1 Block Diagram of Flash Memory............................................................................ 558 Figure 18.2 Mode Transition for Flash Memory ........................................................................ 559 Figure 18.3 Flash Memory Configuration .................................................................................. 561 Figure 18.4 Block Division of User MAT (1) ............................................................................ ...
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Section 20 Power-Down Modes Figure 20.1 Mode Transition Diagram ....................................................................................... 667 Figure 20.2 Medium-Speed Mode Timing ................................................................................. 670 Figure 20.3 Software Standby Mode Application Example ....................................................... 673 Figure 20.4 Hardware Standby Mode Timing ............................................................................ 674 Section 22 Electrical Characteristics Figure ...
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Rev. 2.00 Aug. 03, 2005 Page xxxvi of xlii ...
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Section 1 Overview Table 1.1 H8S/2189R Group Pin Assignment in Each Operating Mode .................................. 4 Table 1.2 Pin Functions .......................................................................................................... 10 Section 2 CPU Table 2.1 Instruction Classification ........................................................................................ 33 Table 2.2 Operation Notation ................................................................................................. 34 Table 2.3 Data Transfer ...
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Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (H8S/2140B Group Compatible Vector Mode) ...................................................... 98 Table 5.5 Interrupt Sources, Vector Addresses, and Interrupt Priorities (Extended Vector Mode) ...................................................................................... 102 Table 5.6 Interrupt Control Modes ....................................................................................... 105 Table 5.7 Interrupts ...
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Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.1 TPU Functions ...................................................................................................... 269 Table 11.2 Pin Configuration.................................................................................................. 271 Table 11.3 CCLR2 to CCLR0 (channel 0) ............................................................................. 274 Table 11.4 CCLR2 to CCLR0 (channels 1 and 2) .................................................................. 274 Table 11.5 ...
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Section 14 Serial Communication Interface (SCI, IrDA) Table 14.1 Pin Configuration.................................................................................................. 391 Table 14.2 Relationships between N Setting in BRR and Bit Rate B..................................... 405 Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 406 ...
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Table 18.4 Parameters and Target Modes............................................................................... 576 Table 18.5 On-Board Programming Mode Setting ................................................................. 586 Table 18.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI......... 588 Table 18.7 Executable MAT................................................................................................... 606 Table 18.8 (1) Usable Area for Programming in ...
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Appendix Table A.1 I/O Port States in Each Pin State........................................................................... 757 Rev. 2.00 Aug. 03, 2005 Page xlii of xlii ...
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Overview • 16-bit high-speed H8S/2000 CPU Upward-compatible with the H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions • Various peripheral functions 8-bit PWM timer (PWM) 14-bit PWM timer (PWMX) 16-bit timer pulse ...
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Section 1 Overview 1.2 Internal Block Diagram VCC VCC VCC VCL VSS VSS VSS VSS VSS X1 X2 RES XTAL EXTAL MD2 MD1 MD0 FWE NMI STBY RESO ETRST PE0 PE1*/ETCK PE2*/ETDI PE3*/ETDO PE4*/ETMS P90 /IRQ2/ADTRG P91/IRQ1 P92/IRQ0 P93/IRQ12 P94/IRQ13 ...
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Pin Description 1.3.1 Pin Assignments 108 107 106 105 109 P12 P11 110 111 VSS 112 P10 113 PB7/WUE7 114 PB6/WUE6 115 PB5/WUE5 116 PB4/WUE4 117 PB3/WUE3 118 PB2/WUE2 PB1/WUE1 119 PB0/WUE0/LSMI 120 P30 121 P31 122 P32 123 ...
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Section 1 Overview 1.3.2 Pin Assignment in Each Operating Mode Table 1.1 H8S/2189R Group Pin Assignment in Each Operating Mode Pin No. Single-Chip Mode TFP-144 Mode 2 1 VCC 2 P43/TMCI1/ExSCK1 3 P44/TMO1 4 P45/TMRI1 5 P46/PWX0 6 P47/PWX1 7 ...
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Pin No. Single-Chip Mode TFP-144 Mode 2 28 PE4*/ETMS 29 PE3*/ETDO 30 PE2*/ETDI 31 PE1*/ETCK 32 PE0 33 (N) PA7/KIN15 34 (N) PA6/KIN14 35 (N) PA5/KIN13 36 VCC 37 (N) PA4/KIN12 38 (N) PA3/KIN11 39 (N) PA2/KIN10 40 (N) PA1/KIN9 ...
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Section 1 Overview Pin No. Single-Chip Mode TFP-144 Mode 2 57 (N) PG1/ExIRQ9/ExTMCI1 58 (N) PG0/ExIRQ8/ExTMCI0 59 PD7/TIOCB2/TCLKD 60 PD6/TIOCA2 61 PD5/TIOCB1/TCLKC 62 PD4/TIOCA1 63 PD3/TIOCD0/TCLKB 64 PD2/TIOCC0/TCLKA 65 PD1/TIOCB0 66 PD0/TIOCA0 67 AVSS 68 P70/ExIRQ0/AN0 69 P71/ExIRQ1/AN1 70 P72/ExIRQ2/AN2 ...
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Pin No. Single-Chip Mode TFP-144 Mode 2 86 VCC 87 PC7/WUE15 88 PC6/WUE14 89 PC5/WUE13 90 PC4/WUE12 91 PC3/WUE11 92 PC2/WUE10 93 PC1/WUE9 94 PC0/WUE8 95 VSS 96 P27/PW15 97 P26/PW14 98 P25/PW13 99 P24/PW12 100 P23/PW11 101 P22/PW10 102 ...
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Section 1 Overview Pin No. Single-Chip Mode TFP-144 Mode 2 115 PB5/WUE5 116 PB4/WUE4 117 PB3/WUE3 118 PB2/WUE2 119 PB1/WUE1 120 PB0/WUE0 121 P30 122 P31 123 P32 124 P33 125 P34 126 P35 127 P36 128 P37 129 P80 ...
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Pin No. Single-Chip Mode TFP-144 Mode 2 RESO 142 143 XTAL 144 EXTAL Notes: (N) indicates that the output type of the pin is NMOS push-pull or NMOS open drain. Not supported by the system development tool (emulator). * Section ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.2 Pin Functions Type Symbol Pin No. Power VCC 1, 36, supply 86 VCL 13 VSS 7, 42, 95, 111, 139 Clock XTAL 143 EXTAL 144 φ 18 EXCL 18 ExEXCL 16 X2 ...
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Type Symbol Pin No. Interrupts NMI 11 IRQ15 to 17, 19, IRQ0 20, 21 50, 85, 84, 135, 134, 133, 24, 23, 22 ExIRQ15 ExIRQ0 138, 14 ETRST* 2 H-UDI 27 ...
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Section 1 Overview Type Symbol Pin No. PWM timer PW15 103 (PWM) PW8 ExPW15 ExPW12 14-bit PWM PWX1 6 timer PWX0 5 (PWMX) 16-bit free FTCI 78 running FTOA 79 timer (FRT) FTOB ...
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Type Symbol Pin No. 8-bit timer TMRI0 138 (TMR_0, TMRI1 4 TMR_1, TMIX 78 TMR_X, TMR_Y) TMIY 80 ExTMIX 56 ExTMIY 55 Serial TxD1 133 communi- TxD2 136 cation ExTxD1 16 interface (SCI_1, RxD1 134 SCI_2) RxD2 137 ExRxD1 15 ...
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Section 1 Overview Type Symbol Pin No. KIN15 to Keyboard 33 to 35, KIN8 control KIN7 to KIN0 WUE15 WUE8 WUE7 to 113 to 120 WUE0 A/D AN7 to 75 ...
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Type Symbol Pin No. I/O ports P17 to P10 104 to 110, 112 P27 to P20 96 to 103 P37 to P30 128 to 121 P47 to P40 138 to 136 P52 to P50 ...
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Section 1 Overview Type Symbol Pin No. I/O ports PG7 PG0 Notes: 1. Pins PE4 to PE1 are not supported by the system development tool (emulator). 2. Following precautions are required on the power-on reset signal ...
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The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16 Mbytes linear address space, and ...
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Section 2 CPU 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) 32 ÷ 16-bit register-register divide: 20 states (DIVXU.W) • Two CPU operating modes Normal mode* Advanced mode • Power-down state Transition ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers Eight 16-bit extended registers and one 8-bit control register have been added. • Extended ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal* and advanced. Normal mode* supports a maximum 64 Kbytes address space. Advanced mode supports a maximum 16 Mbytes address space. The mode is selected by ...
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Stack structure In normal mode, when the program counter (PC) is pushed onto the stack in a subroutine call in normal mode, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are ...
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Section 2 CPU 2.2.2 Advanced Mode • Address space Linear access to a maximum address space of 16 Mbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also ...
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The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a ...
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Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64 Kbytes address space in normal mode, and a maximum 16 Mbytes (architecturally 4 Gbytes) ...
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Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. These are classified into two types of registers: general registers and control registers. Control registers refer to a 24-bit program counter (PC), an 8-bit extended control ...
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Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a ...
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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When ...
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Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the ...
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Bit Bit Name Initial Value 2 Z Undefined 1 V Undefined 0 C Undefined 2.4.5 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, ...
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Section 2 CPU 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En [Legend] ERn : General register General register General register R RnH : General register RH RnL ...
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Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address ...
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Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* 5 LDM* , STM* MOVFPE* ...
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Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol ...
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Table 2.3 Data Transfer Instructions 1 Instruction Size* Function (EAs) → Rd, Rs → (EAd) MOV B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B ...
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Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L SUB Performs addition or subtraction on data in two general registers immediate data and ...
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Table 2.4 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ...
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Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ...
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Table 2.6 Shift Instructions Instruction Size* Function Rd (shift) → Rd SHAL B/W/L SHAR Performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. Rd (shift) → Rd SHLL B/W/L SHLR Performs a ...
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Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate ...
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Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the ...
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Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc – Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) ...
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Table 2.9 System Control Instructions Instruction Size* Function TRAPA – Starts trap-instruction exception handling. RTE – Returns from an exception-handling routine. SLEEP – Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR LDC B/W Moves the ...
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Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B – else next ≠ 0 then EEPMOV.W – else next: Transfers a data block. Starting from the address set in ...
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Basic Instruction Formats The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of ...
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Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register ...
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Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address ...
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Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction 24 bits (@aa:24) address Note: Not available in this LSI. * 2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 ...
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Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. The upper bits of the 8-bit absolute address are ...
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Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode*, the upper eight bits of the effective address are ignored in order to generate a 16-bit address. Note: ...
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Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate Note: * Not available in this LSI. Effective Address Calculation PC contents Sign extension Memory contents Memory contents Rev. 2.00 Aug. 03, 2005 Page 51 of ...
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Section 2 CPU 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this ...
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End of exception handling Exception-handling state RES = high *1 Reset state From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. goes low. A transition can also be made to the ...
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Section 2 CPU 2.9 Usage Notes 2.9.1 Note on TAS Instruction Usage To use the TAS instruction, use registers ER0, ER1, ER4, and ER5. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers. ...
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EEPMOV Instruction 1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4*, which starts from the address indicated by ER5, to the address indicated by ER6. ER5 ER5 + R4 2. Set R4 ...
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Section 2 CPU Rev. 2.00 Aug. 03, 2005 Page 56 of 766 REJ09B0223-0200 ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports three operating modes (modes 2, 4, and 6). The operating mode is determined by the setting of the mode pins (MD2, MD1, and MD0). Table 3.1 shows the ...
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Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating modes. • Mode control register (MDCR) • System control register (SYSCR) • Serial timer control register (STCR) • System control register 3 (SYSCR3) 3.2.1 ...
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System Control Register (SYSCR) SYSCR monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables access to the on-chip peripheral module registers, and enables or disables the on-chip RAM address space. ...
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Section 3 MCU Operating Modes Bit Bit Name Initial Value 1 KINWUE 0 0 RAME 1 Rev. 2.00 Aug. 03, 2005 Page 60 of 766 REJ09B0223-0200 R/W Description R/W Keyboard Control Register Access Enable When the RELOCATE bit is cleared ...
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Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Bit Bit Name Initial Value 7 IICS 0 6 IICX1 0 5 ...
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Section 3 MCU Operating Modes Bit Bit Name Initial Value 4 IICE 0 Rev. 2.00 Aug. 03, 2005 Page 62 of 766 REJ09B0223-0200 R/W Description 2 R Master Enable When the RELOCATE bit is cleared to 0, enables ...
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Bit Bit Name Initial Value 3 FLSHE 0 2 — ICKS1 0 0 ICKS0 0 R/W Description R/W Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FCCS, FPCS, FECS, FKEY, FMATS, and ...
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Section 3 MCU Operating Modes 3.2.4 System Control Register 3 (SYSCR3) SYSCR3 selects the register map and interrupt vector. Bit Bit Name Initial Value 7 — EIVS RELOCATE — All 0 Note: ...
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Operating Mode Descriptions 3.3.1 Mode 2 The CPU can access a 16-Mbyte address space in either advanced mode or single-chip mode. The on-chip ROM is enabled. Section 3 MCU Operating Modes Rev. 2.00 Aug. 03, 2005 Page 65 of ...
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Section 3 MCU Operating Modes 3.4 Address Map Figure 3.1 shows the address map in each operating mode. Rev. 2.00 Aug. 03, 2005 Page 66 of 766 REJ09B0223-0200 Mode 2 (EXPE = 0) Advanced mode Single-chip mode ROM: 1 Mbyte ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling Table 4.2 Exception Handling Vector Table (H8S/2140B Group Compatible Vector Mode) Exception Source Reset Reserved for system use Direct transition External interrupt (NMI) Trap instruction (four sources) Reserved for system use External interrupt IRQ0 IRQ1 IRQ2 ...
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Exception Source Internal interrupt* External interrupt IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Internal interrupt* Note: * For details on the internal interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Table. Section 4 Exception Handling Vector Address ...
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Section 4 Exception Handling Table 4.3 Exception Handling Vector Table (Extended Vector Mode) Exception Source Reset Reserved for system use Direct transition External interrupt (NMI) Trap instruction (four sources) Reserved for system use External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 ...
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Exception Source Internal interrupt* External interrupt IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Internal interrupt* Note: * For details on the internal interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Table. Section 4 Exception Handling Vector Addresses ...
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Section 4 Exception Handling 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin ...
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RES Internal address bus Internal read signal Internal write signal Internal data bus (1) Reset exception handling vector address ( H'000000 ( H'000002 (2) Start address (contents of reset exception handling vector address) (3) Start address ...
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Section 4 Exception Handling 4.4 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ15 to IRQ0, KIN15 to KIN0, and WUE15 to WUE0) and internal interrupt ...
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Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal mode SP Note: * Ignored on return. Figure 4.2 Stack Status after Exception Handling CCR CCR* SP ...
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Section 4 Exception Handling 4.7 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack ...
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Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control ...
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Section 5 Interrupt Controller SYSCR3 SYSCR NMI input IRQ input KIN input WUE input Internal interrupt sources SWDTEND to IBFI3 Interrupt controller [Legend] : Interrupt control register ICR : IRQ sense control register ISCR : IRQ enable register IER ISR ...
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Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Symbol I/O NMI Input IRQ15 to IRQ0, Input ExIRQ15 to ExIRQ0 KIN15 to KIN0 Input WUE15 to WUE8 Input WUE7 to WUE0 Input Function ...
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Section 5 Interrupt Controller 5.3 Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR). For details on system control register 3 (SYSCR3), see section 3.2.4, ...
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Table 5.2 Correspondence between Interrupt Source and ICR (H8S/2140B Group Compatible Vector Mode: EIVS = 0) Bit Bit Name ICRA 7 ICRn7 IRQ0 6 ICRn6 IRQ1 5 ICRn5 IRQ2, IRQ3 4 ICRn4 IRQ4, IRQ5 3 ICRn3 IRQ6, IRQ7 2 ...
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Section 5 Interrupt Controller 5.3.2 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ0. • ISCR16H Bit Bit Name Initial ...
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ISCR16L Bit Bit Name Initial Value 7 IRQ11SCB 0 6 IRQ11SCA 0 5 IRQ10SCB 0 4 IRQ10SCA 0 3 IRQ9SCB 0 2 IRQ9SCA 0 1 IRQ8SCB 0 0 IRQ8SCA 0 • ISCRH Bit Bit Name Initial Value 7 IRQ7SCB ...
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Section 5 Interrupt Controller • ISCRL Bit Bit Name Initial Value 7 IRQ3SCB 0 6 IRQ3SCA 0 5 IRQ2SCB 0 4 IRQ2SCA 0 3 IRQ1SCB 0 2 IRQ1SCA 0 1 IRQ0SCB 0 0 IRQ0SCA 0 Rev. 2.00 Aug. 03, 2005 ...
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IRQ Enable Registers (IER16, IER) The IER registers enable and disable interrupt requests IRQ15 to IRQ0. • IER16 Bit Bit Name Initial Value 7 IRQ15E 0 6 IRQ14E 0 5 IRQ13E 0 4 IRQ12E 0 3 IRQ11E 0 2 ...
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Section 5 Interrupt Controller 5.3.4 IRQ Status Registers (ISR16, ISR) The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests. • ISR16 Bit Bit Name Initial Value 7 IRQ15F 0 6 IRQ14F 0 5 ...
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ISR Bit Bit Name Initial Value 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F 0 4 IRQ4F 0 3 IRQ3F 0 2 IRQ2F 0 1 IRQ1F 0 0 IRQ0F 0 Note: Only 0 can be written for clearing the ...
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Section 5 Interrupt Controller 5.3.5 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR, WUEMRB) The KMIMR, KMIMR, WUEMR, and WUEMRB registers enable or disable key-sensing interrupt inputs (KIN15 to KIN0) and wake-up event interrupt inputs ...
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WUEMR Bit Bit Name Initial Value 7 WUEMR15 1 6 WUEMR14 1 5 WUEMR13 1 4 WUEMR12 1 3 WUEMR11 1 2 WUEMR10 1 1 WUEMR9 1 0 WUEMR8 1 • WUEMRB Bit Bit Name Initial Value 7 WUEMR7 ...
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Section 5 Interrupt Controller Figure 5.2 shows the relation between the IRQ7 and IRQ6 interrupts, KIN15 to KIN0 interrupts, WUE7 to WUE0 interrupts, KMIMR, KMIMRA, and WUEMRB in H8S/2140B Group compatible vector mode. The relation in extended vector mode is ...
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KMIMR0 (Initial value of 1) P60/KIN0 KMIMR5 (Initial value of 1) P65/KIN5 KMIMR6 (Initial value of 1) P66/KIN6/IRQ6 P52/ExIRQ6 KMIMR7 (Initial value of 1) P67/KIN7/IRQ7 ISS7 P42/ExIRQ7 KMIMR8 (Initial value of 1) PA0/KIN8 KMIMR15 (Initial value of 1) PA7/KIN15 WUEMR0 ...
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Section 5 Interrupt Controller 5.3.6 IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR) ISSR16 and ISSR select the IRQ15 to IRQ0 interrupt external input from IRQ15 to IRQ0 pins and ExIRQ15 to ExIRQ0 pins. • ...
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ISSR Bit Bit Name Initial Value 7 ISS7 0 ISS5 0 4 ISS4 0 3 ISS3 0 2 ISS2 0 1 ISS1 0 0 ISS0 0 R/W Description R/W 0: P67/IRQ7 is selected 1: P42/ExIRQ7 ...
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Section 5 Interrupt Controller 5.4 Interrupt Sources 5.4.1 External Interrupt Sources The interrupt sources of external interrupts are NMI, IRQ15 to IRQ0, KIN15 to KIN0 and WUE15 to WUE0. These interrupts can be used to restore this LSI from software ...
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IRQn ISSm ExIRQn and Note: Switching between the IRQ6 and ExIRQ6 pins is controlled by the EIVS bit in SYSCR3. Figure 5.4 Block Diagram of Interrupts IRQ15 ...
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Section 5 Interrupt Controller • Extended vector mode (EIVS = 1 in SYSCR3) Interrupts KIN15 to KIN8, KIN7 to KIN0, WUE15 to WUE8, and WUE7 to WUE0 each form a group. The interrupt exception handling for an interrupt request ...
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Internal Interrupt Sources Internal interrupts issued from the on-chip peripheral modules have the following features: • For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling ...
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Section 5 Interrupt Controller 5.5 Interrupt Exception Handling Vector Tables Tables 5.4 and 5.5 list interrupt exception handling sources, vector addresses, and interrupt priorities. H8S/2140B Group compatible vector mode or extended vector mode can be selected for the vector addresses ...
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Origin of Interrupt Source Name A/D converter ADI (A/D conversion end) — Reserved for system use Reserved for system use Reserved for system use External pin Reserved for system use WUE15 to WUE8 TPU_0 TGI0A (TGR0A input capture/compare match) TGI0B ...
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Section 5 Interrupt Controller Origin of Interrupt Source Name External pin IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 TMR_0 CMIA0 (Compare match A) CMIB0 (Compare match B) OV10 (Overflow) Reserved for system use TMR_1 CMIA1 (Compare match A) CMIB1 ...
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Origin of Interrupt Source Name SCI_2 ERI2 (Reception error 2) RXI2 (Reception completion 2) TXI2 (Transmission data empty 2) TEI2 (Transmission end 2) IIC_0 IICI0 (1-byte transmission/reception completion) Reserved for system use IIC_1 IICI1 (1-byte transmission/reception completion) Reserved for system ...
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Section 5 Interrupt Controller Table 5.5 Interrupt Sources, Vector Addresses, and Interrupt Priorities (Extended Vector Mode) Origin of Interrupt Source Name External pin NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Reserved for system use WDT_0 WOVI0 (Interval ...
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Origin of Interrupt Source Name TPU_1 TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TGI1V (Overflow 1) TGI1U (Underflow 1) TPU_2 TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TGI2V (Overflow 1) TGI2U (Underflow 2) Reserved ...
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Section 5 Interrupt Controller Origin of Interrupt Source Name TMR_1 CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use TMR_X CMIAY (Compare match A) TMR_Y CMIBY (Compare match B) OVIY (Overflow) ICIX (Input capture) CMIAX ...
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Origin of Interrupt Source Name IIC_1 IICI1 (1-byte transmission/reception completion) Reserved for system use — Reserved for system use 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode ...
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Section 5 Interrupt Controller Figure 5.6 shows a block diagram of the priority determination circuit. Interrupt source Interrupt control modes Figure 5.6 Block Diagram of Interrupt Control Operation Rev. 2.00 Aug. 03, 2005 Page 106 of 766 REJ09B0223-0200 I UI ...
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Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 5.7 shows ...
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Section 5 Interrupt Controller Table 5.8 Operations and Control Signal Functions in Each Interrupt Control Mode Setting Interrupt Control Mode INTM1 INTM0 [Legend] Ο: Interrupt operation control is performed IM: Used as an interrupt mask ...
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An interrupt with interrupt control level 1? IRQ0 Yes Figure 5.7 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 Program execution state Interrupt generated? Yes Yes NMI No No Yes No IRQ0 No Yes IRQ1 Yes ...
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Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for interrupt requests other than NMI by comparing the I and UI bits in CCR in the CPU, and ...
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Figure 5.9 shows a flowchart of the interrupt acceptance operation interrupt source occurs when the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. 2. According to the interrupt ...
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Section 5 Interrupt Controller An interrupt with interrupt control level 1? IRQ0 Yes Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 Rev. 2.00 Aug. 03, 2005 Page 112 of 766 REJ09B0223-0200 Program execution state ...
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Interrupt Exception Handling Sequence Figure 5.10 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip ...
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Section 5 Interrupt Controller Figure 5.10 Interrupt Exception Handling Rev. 2.00 Aug. 03, 2005 Page 114 of 766 REJ09B0223-0200 ...
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Interrupt Response Times Table 5.9 shows interrupt response times − the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. Table 5.9 Interrupt Response Times No. Execution Status 1 Interrupt ...
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Section 5 Interrupt Controller 5.7 Usage Notes 5.7.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable ...
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Instructions for Disabling Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit ...
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Section 5 Interrupt Controller 5.7.5 External Interrupt Pin in Software Standby Mode and Watch Mode • When the pins (IRQ15 to IRQ0, ExIRQ15 to ExIRQ0, KIN15 to KIN0, and WUE15 to WUE0) are used as external input pins in software ...
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Section 6 Bus Controller (BSC) Since this LSI does not have an externally extended function, it does not have an on-chip bus controller (BSC). Considering the software compatibility with similar products, you must be careful to set appropriate values to ...
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Section 6 Bus Controller (BSC) 6.1.2 Wait State Control Register (WSCR) Bit Bit Name Initial Value ABW 1 4 AST 1 3 WMS1 0 2 WMS0 0 1 WC1 1 0 WC0 1 ...
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Table 7 summary of the port functions. The pins of each port also function as input/output pins of peripheral modules and interrupt input pins. Each input/output port includes a data direction register (DDR) that controls input/output and data ...
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Section 7 I/O Ports Port Description Port 3 General I/O port Port 4 General I/O port also functioning as interrupt input, PWMX output, TMR_0, TMR_1, SCI_1, SCI_2, and IIC_1 inputs/outputs Port 5 General I/O port also functioning as interrupt input, ...
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Port Description Port 7 General input port also functioning as interrupt input and A/D converter analog input Port 8 General I/O port also functioning as interrupt input, SCI_1, IrDA interface, and IIC_1 inputs/outputs Port 9 General I/O port also functioning ...
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Section 7 I/O Ports Port Description Port B General I/O port also functioning as wake-up event input Port C General I/O port also functioning as wake-up event input Port D General I/O port also functioning as TPU input/output Port E ...
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Port Description Port F General I/O port also functioning as interrupt input, and PWM and TMR_X outputs Port G General I/O port also interrupt input, TMR_0, TMR_1, TMR_X, and TMR_Y inputs, and IIC_0 and IIC_1 inputs/outputs Note: Not supported in ...
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Section 7 I/O Ports 7.1 Port 1 Port 8-bit I/O port. Port 1 has a built-in input pull-up MOS that can be controlled by software. Port 1 has the following registers. • Port 1 data direction register ...
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Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Bit Name Initial Value 7 P17DR 0 6 P16DR 0 5 P15DR 0 4 P14DR 0 3 P13DR 0 2 P12DR 0 1 P11DR ...
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Section 7 I/O Ports 7.1.4 Pin Functions • P17, P16, P15, P14, P13, P12, P11, P10 The function of port 1 pins is switched as shown below according to the P1nDDR bit. P1nDDR Pin function Note ...
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Port 2 Port 8-bit I/O port. Port 2 pins also functions as PWM output pins. Port 2 has a built-in input pull-up MOS that can be controlled by software. Port 2 has the following registers. • ...
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Section 7 I/O Ports 7.2.2 Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit Bit Name Initial Value 7 P27DR 0 6 P26DR 0 5 P25DR 0 4 P24DR 0 3 P23DR 0 2 ...
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Pin Functions • P27/PW15, P26/PW14 The function of port 2 pins is switched as shown below according to the combination of the PWMAS bit in PTCNT0, the OEm bit in PWOERB of PWM, and the P2nDDR bit. PWMAS P2nDDR ...
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Section 7 I/O Ports 7.2.5 Port 2 Input Pull-Up MOS Port 2 has a built-in input pull-up MOS that can be controlled by software. Table 7.3 summarizes the input pull-up MOS states. Table 7.3 Port 2 Input Pull-Up MOS States ...
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Port 3 Port 8-bit I/O port. Port 3 has a built-in input pull-up MOS that can be controlled by software. Port 3 has the following registers. • Port 3 data direction register (P3DDR) • Port 3 ...
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Section 7 I/O Ports 7.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Bit Name Initial Value 7 P37DR 0 6 P36DR 0 5 P35DR 0 4 P34DR 0 3 P33DR 0 2 ...
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Pin Functions • P37, P36, P35, P34, P33, P32, P31, P30 P3nDDR Pin function Note 7.3.5 Port 3 Input Pull-Up MOS Port 3 has a built-in input pull-up MOS that can be controlled by ...
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Section 7 I/O Ports 7.4 Port 4 Port 8-bit I/O port. Port 4 pins also function as interrupt input, PWMX output, TMR_0, TMR_1, SCI_1, SCI_2, and IIC_1, input/output pins. The output format for P42 and SCK2 is ...
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Port 4 Data Register (P4DR) P4DR stores output data for the port 4 pins. Bit Bit Name Initial Value 7 P47DR 0 6 P46DR 0 5 P45DR 0 4 P44DR 0 3 P43DR 0 2 P42DR 0 1 P41DR ...
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Section 7 I/O Ports • P45/TMRI1 The pin function is switched as shown below according to the P45DDR bit. When the CCLR1 and CCLR0 bits in TCR of TMR_1 are set to 1, this pin is used as the TMRI1 ...
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P42/ExIRQ7/TMRI0/SCK2/SDA1 The pin function is switched as shown below according to the combination of the SDA1AS and SDA1BS bits in PTCNT1, ICE bit in ICCR of IIC_1, CKE1 and CKE0 bits in SCR of SCI_2, C/A bit in SMR, ...
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Section 7 I/O Ports • P40/TMCI0/TxD2 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_2 and the P40DDR bit. When the TMI0S bit in PTCNT0 is cleared to 0 ...
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Port 5 Port 3-bit I/O port. Port 5 pins also function as interrupt input pins, IIC_0 and SCI_1 input/output pins, TMR_Y output pin, and the external sub-clock input pin. The output format for P52 is NMOS ...
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Section 7 I/O Ports 7.5.3 Pin Functions • P52/ExIRQ6/SCL0 The pin function is switched as shown below according to the combination of the SCL0AS and SCL0BS bits in PTCNT1, ICE bit in ICCR of IIC_1, and the P52DDR bit. When ...
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P50/ExEXCL/ExTxD1 The pin function is switched as shown below according to the combination of the SCD1S bit in PTCNT2, the TE bit in SCR of SCI_1, EXCLS bit in PTCNT0, EXCLE bit in LPWRCR, and the P50DDR bit. To ...
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Section 7 I/O Ports 7.6 Port 6 Port 8-bit I/O port. Port 6 pins also function as the interrupt input pin, TMR_Y, keyboard and noise cancel input pins, FRT, and TMR_X input/output pin. Port 6 can change ...
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Port 6 Data Register (P6DR) P6DR stores output data for the port 6 pins. Bit Bit Name Initial Value 7 P67DR 0 6 P66DR 0 5 P65DR 0 4 P64DR 0 3 P63DR 0 2 P62DR 0 1 P61DR ...
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Section 7 I/O Ports 7.6.4 Noise Canceller Enable Register (P6NCE) P6NCE enables or disables the noise cancel circuit at port 6. Bit Bit Name Initial Value 7 P67NCE 0 6 P66NCE 0 5 P65NCE 0 4 P64NCE 0 3 P63NCE ...
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Noise Cancel Cycle Setting Register (P6NCCS) P6NCCS controls the sampling cycles of the noise canceller. Bit Bit Name Initial Value Undefined 2 P6NCCK2 0 1 P6NCCK1 0 0 P6NCCK0 0 R/W Description R/W Reserved The ...
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Section 7 I/O Ports /2, /32, /8192, /65536, /131072, /262144 Sampling clock selection t Pin Latch Latch input t Sampling clock P6n Input 1 expected P6n Input 0 expected P6n Input ( Rev. 2.00 Aug. 03, ...
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System Control Register 2 (SYSCR2) SYSCR2 controls the port 6 input level selection and the current specifications for the port 6 input pull-up MOSs. Bit Bit Name Initial Value 7 KWUL1 0 6 KWUL0 0 5 P6PUE 0 4 ...
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Section 7 I/O Ports • P66/IRQ6/KIN6/FTOB The function of port 6 pins is switched as shown below according to the combination of the OEB bit in TOCR of FRT and the P66DDR bit. When the KMIMR6 bit in KMIMR of ...
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P63/KIN3/FTIB The function of port 6 pins is switched as shown below according to the P63DDR bit. When the ICIBE bit in TIER of FRT is set to 1, this pin can be used as the FTIB input pin. ...
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Section 7 I/O Ports • P60/KIN0/FTCI/TMIX The function of port 6 pins is switched as shown below according to the P60DDR bit. When the CKS1 and CKS0 bits in TCR of FRT are both set to 1, this pin can ...
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Port 7 Port 8-bit input port. Port 7 pins also function as the interrupt input pins and A/D converter analog input pins. Port 7 has the following register. • Port 7 input data register (P7PIN) 7.7.1 ...
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Section 7 I/O Ports 7.7.2 Pin Functions • P77/AN7, P76/AN6 Pin function Note • P75/ExIRQ5/AN5, P74/ExIRQ4/AN4, P73/ExIRQ3/AN3, P72/ExIRQ2/AN2, P71/ExIRQ1/AN1, P70/ExIRQ0/AN0 When the ISS0n bit in ISSR and the IRQnE bit in IER of the interrupt controller ...
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Port 8 Port 7-bit I/O port. Port 8 pins also function as the interrupt input pins, SCI_1 and IIC_1 input/output pins. The output format for P86 and SCK1 is NMOS push-pull output. The output format for ...
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Section 7 I/O Ports 7.8.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit Bit Name Initial Value P86DR 0 5 P85DR 0 4 P84DR 0 3 P83DR 0 2 ...