HD6417041ACF28V Renesas Electronics America, HD6417041ACF28V Datasheet - Page 23

IC SUPERH MPU ROMLESS 144QFP

HD6417041ACF28V

Manufacturer Part Number
HD6417041ACF28V
Description
IC SUPERH MPU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Datasheet

Specifications of HD6417041ACF28V

Core Processor
SH-2
Core Size
32-Bit
Speed
28MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417041ACF28V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section
Page
Description
Class
Port
control
SCI
A/D
converter
control
I/O Port
Notes: 1. There are instances where bus right release and transition to software standby mode
Pin Function
2. I: Input, O: Output, H: High-level output, L: Low-level output, Z: High impedance,
*1 If the standby control register port high-impedance bits are set to 1, output pins become
*2 A21–A18 will become input ports after power-on reset.
*3 Input in the SH7044/SH7045 F-ZTAT version.
*4 General use I/O ports PAn, PBn, PCn, PDn, and PEn, as well as pins multiplexed with
Pin Name
POE0–POE3
SCK0–SCK1
TXD0–TCD1
RXD0–RXD1
ADTRG
AN0–AN7
PA0–PA15
PB0–PB9
PC0–PC15
PD0–PD15
PE0–PE8–PE10
PE9,PE11–PE15
PF0–PF7
The initial pin states depend on the mode. See section 18, Pin Function Controller
occur simultaneously due to the timing between BREQ and internal operations. In such
cases, standby mode results, but the standby state may be different.
(PFC), for details.
K: Input pin with high impedance, output pin mode maintained.
high impedance.
them, are unstable during the RES setup time (t
goes to low level.
Power-On Manual Standby Sleep Release
Z *
Z *
Z *
Z *
Z *
Z
Z *
Z *
Z
4
4
4
4
4
4
4
Reset
I
I/O
O
I
I
I
I/O
I/O
I
Pin modes
Z
Z
O *
Z
Z
Z
K *
Z
Z
Power-Down Bus Right
1
1
RESS
I
I/O
O
I
I
I
K
K
I
) immediately after the RES pin
I
I/O
O
I
I
I
I/O
I/O
I
Standby in Bus
Right Release
Z
Z
O *
Z
Z
Z
K *
Z
Z
1
1

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