M30873FHBGP#U3 Renesas Electronics America, M30873FHBGP#U3 Datasheet - Page 170

• Manufacturer Part Number: M30873FHBGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30873FHBGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 146 of 587
Figure 13.7
<When using repeat transfer>
<When using repeat transfer>
i = 0, 1
NOTES:
DMD0 register: bits MD01 and MD00 = 00b
DMiSL register: bits DSEL4 to DSEL0
DMAi register
DSAi register
DRAi register
DCTi register
DRCi register
DMD0 register: bits MD01 and MD00
1. When setting the DMiSL register, write a 1 to the DRQ bit.
2. When the INT interrupts are selected as a DMA request source, do not write a 1 to the DCTi register. If the DCTi register is
3. Wait six CPU clock cycles or more by a program to set bits MDi1 and MDi0 to 01b or 11b after setting the DMiSL register.
4. When a DMA transfer is started by the software trigger, set both the DSR and DRQ bit in the DMiSL register to 1 at the
1, do not generate a DMA request when writing 01b or 11b to bits MDi1 and MDi0.
same time.
Register Settings When Using DMA0 or DMA1
used as DMAi request source
used as DMAi request source
Start the peripheral function
Set the peripheral function
bits MD11 and MD10 = 00b
BW0 bit
RW0 bit
bits MD11 and MD10
BW1 bit
RW1 bit
DSR bit = 0
DRQ bit = 1
Start
End
Set the control registers of the peripheral function,
but do not yet start.
DMA disabled for channel 0
DMA disabled for channel 1
DMA request source select bits
DMA requested
Set an incremented source address or
incremented destination address
Set a fixed source address or
fixed destination address
Set an incremented source address or
incremented destination address
Set the number of transfers
Set the number of transfers, which is to be
reloaded
Transfer mode select bits for channel 0
Transfer unit select bit for channel 0
Transfer direction select bit for channel 0
Transfer mode select bits for channel 1
Transfer unit select bit for channel 1
Transfer direction select bit for channel 1
(note 4)
(2)
Write with LDC instruction
Write with LDC instruction
Write with LDC instruction
(note 3)
Write with LDC instruction
(note 1)
Write with LDC instruction
Write with LDC instruction
13. DMAC