M30627FJPGP#U9C Renesas Electronics America, M30627FJPGP#U9C Datasheet - Page 151
![IC M16C/62P MCU FLASH 128LQFP](/photos/12/30/123024/m30627fjpgp_u9c_sml.jpg)
M30627FJPGP#U9C
Manufacturer Part Number
M30627FJPGP#U9C
Description
IC M16C/62P MCU FLASH 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30627FJPGP#U9C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30627FJPGP#U9CM30627FJPGP#U3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
14.2
Table 14.2
— : This condition does not exist.
Table 14.3
NOTES:
8-bit Transfers
(DMBIT= 1)
16-bit Transfers
(DMBIT= 0)
k
Any combination of even or odd transfer read and write addresses is possible. Table 14.2 lists the DMA Transfer
Cycles. Table 14.3 lists the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles × j + No. of write cycles × k
j
Transfer Unit
1. Depends on the set value of CSE register.
2. Depends on the set value of PM20 bit in the PM2 register.
No Wait
DMA Transfer Cycles
Internal ROM,
Jan 10, 2006
1
1
RAM
DMA Transfer Cycles
Coefficient j, k
Internal Area
With
Wait
16-bit
(BYTE= L)
8-bit
(BYTE = H)
16-bit
(BYTE = L)
8-bit
(BYTE = H)
Bus Width
2
2
Page 134 of 390
1-Wait
(2)
2
2
SFR
Address
Access
Even
Even
Even
Even
2-Wait
Odd
Odd
Odd
Odd
(2)
3
3
Wait
No. of Read
No
1
2
Cycles
Single-Chip Mode
—
—
—
—
1
1
1
2
1-Wait
Separate Bus
2
2
With Wait
No. of Write
2-Wait
Cycles
3
3
—
—
—
—
1
1
1
2
External Area
(1)
3-Wait
4
4
No. of Read
Memory Expansion Mode
Cycles
Microprocessor Mode
1-Wait
1
1
1
1
1
2
2
2
3
3
Multiplex Bus
With Wait
2-Wait
3
3
No. of Write
Cycles
(1)
1
1
1
1
1
2
2
2
14. DMAC
3-Wait
4
4
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