M30843FJFP#U5 Renesas Electronics America, M30843FJFP#U5 Datasheet - Page 79
M30843FJFP#U5
Manufacturer Part Number
M30843FJFP#U5
Description
IC M32C MCU FLASH 512K 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Specifications of M30843FJFP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
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Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
M30843FJFP#U5M30843FJFP#U3
Manufacturer:
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Part Number:
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M
R
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7.2 Setting of Processor Mode
e
E
3
. v
J
2
Table 7.2 Processor Mode after Hardware Reset
Table 7.3 Processor Mode Selected by the PM01 and PM00 bit Settings
0
C
n I
N
V
V
The CNV
mode is selected. Table 7.2 lists processor mode after hardware reset. Table 7.3 lists processor mode
selected by PM01 and PM00 bit settings.
If the PM01 and PM00 bits are rewritten, the mode corresponding to the PM01 and PM00 bits is selected
regardless of CNV
Do not change the PM01 and PM00 bits to "01
mode) when the PM07 to PM02 bits in the PM0 register are being rewritten.
Do not enter microprocessor mode while the CPU is executing a program in the internal ROM.
Do not enter single-chip mode or memory expansion mode from microprocessor mode while the CPU is
executing a program in an external memory space, the same address assigned for the internal ROM.
The internal ROM cannot be accessed, regardless of PM01 and PM00 bit settings, when applying V
the CNVSS pin and generating the hardware reset (hardware reset 1 or low voltage detection reset).
Figures 7.1 and 7.2 show the PM0 register and PM1 register. Figure 7.3 shows a memory map in each
processor mode.
1
9
S
C
O
0 .
8 /
p
B
S
C
t u
T
0
. 1
. 2
1
4
1
P
0
(
E
, 1
M
L
3
G
T
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J
: S
V
d
e
) 2
0
6
u
h
e
C
o r
u
v
1
0 -
. l
e
C
e t
l e
t l
u
1
p i
a
0
1
SS
n i
t c
p
n i
o t
n
, 7
0
e l
e t
o i
0
0
1
1
d
1
o t
(
pin state and the PM01 and PM00 bit settings in the PM0 register determine which processor
x
0
1
0
1
h t
n
2
n r
M
P
2
2
2
2
0
b
h t
e
e r
l a
M
3
0
u
e
2
C
5
s
s
0
R
e
C
0
N
C
c
O
. ) t
SS
a
8 /
V
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B
M
n
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s t i
Page 56
V
, 4
n
S
pin level.
S
c
t o
p
S
a
M
n i
n
p
b
3
n
n i
e
a
2
t o
n
a
M
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M
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d
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b
n i
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e
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g i
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4
4
a
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p
c c
9
e
r e
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y r
o r
5
d
s
e
t a
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c
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s s
o t
p i
e
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x
o t
s s
e
p
P
M
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g
l l a
M
P
, d
a
o r
n i
r o
c i
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o
h t
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n
g
C
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o r
d
e r
s
s i
e
c
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e
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p
e
g
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h
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o
n
o r
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a
a
a
a
d
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M
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e
r o
p i
e
e l
o
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e
w
M
s s
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2
. s
M
M
s s
a
o
" (memory expansion mode) or "11
e
r o
e r
o
o
d
d
f o
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e
M
e
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e
P
o
s
M
d
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7. Processor Mode
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