DF2556FC20DV Renesas Electronics America, DF2556FC20DV Datasheet - Page 636

IC H8S/2556 MCU FLASH 144QFP

DF2556FC20DV

Manufacturer Part Number
DF2556FC20DV
Description
IC H8S/2556 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Datasheets

Specifications of DF2556FC20DV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2556FC20DV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2556FC20DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
Rev. 6.00 Sep. 24, 2009 Page 588 of 928
REJ09B0099-0600
Bit
0
Bit Name
PE
Initial
Value
0
R/W
R/W
Description
Parity Error
Indicates that a parity error has occurred during data field
reception. If a parity error occurs before data field
reception, the IEB immediately enters the wait state and
the PE flag is not set.
If a parity error occurs when the maximum number of
receive bytes in one frame has not been received, the PE
flag is not set. When a parity error occurs, the IEB returns
a NAK to the communications destination unit via the
acknowledge bit. In this case, the communications
destination unit continues retransfer up to the maximum
number of receive bytes in one frame and if the reception
has been completed normally by clearing the parity error,
the PE flag is not set. If the parity error is not cleared when
the reception is terminated before receiving data for the
number of bytes specified by the message length, the PE
flag is set.
In broadcast reception, if a parity error occurs during data
field reception, the IEB enters the wait state immediately
after setting the PE flag.
[Setting condition]
[Clearing condition]
When the parity bit of last data of the data field is not
correct after the maximum number of receive bytes has
been received
When writing 0 after reading PE = 1

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