M30843FJFP#U3 Renesas Electronics America, M30843FJFP#U3 Datasheet - Page 23
![IC M32C MCU FLASH 512K 100LQFP](/photos/12/31/123117/m30843fjfp_u3_sml.jpg)
M30843FJFP#U3
Manufacturer Part Number
M30843FJFP#U3
Description
IC M32C MCU FLASH 512K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Specifications of M30843FJFP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30843FJFP#U3M30843FJFP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M
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2.2 High-Speed Interrupt Registers
2.3 DMAC-Associated Registers
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Registers associated with the high-speed interrupt are as follows:
Registers associated with DMAC are as follows:
1
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2 .
- Flag save register (SVF)
- PC save register (SVP)
- Vector register (VCT)
- DMA mode register (DMD0, DMD1)
- DMA transfer count register (DCT0, DCT1)
- DMA transfer count reload register (DRC0, DRC1)
- DMA memory address register (DMA0, DMA1)
- DMA SFR address register (DSA0, DSA1)
- DMA memory address reload register (DRA0, DRA1)
1
4
2.1.8.5 Register Bank Select Flag (B)
2.1.8.6 Overflow Flag (O)
2.1.8.7 Interrupt Enable Flag (I)
2.1.8.8 Stack Pointer Select Flag (U)
2.1.8.9 Processor Interrupt Priority Level (IPL)
2.1.8.10 Reserved Space
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The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this
flag is set to "1".
The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0".
The I flag enables a maskable interrupt.
Interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag is
set to "0" when an interrupt is acknowledged.
ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1".
The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
When writing to a reserved space, set to "0". When reading, its content is indeterminate.
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2. Central Processing Unit (CPU)