M30845FHGP#U3 Renesas Electronics America, M30845FHGP#U3 Datasheet - Page 136
![IC M32C MCU FLASH 384K 144LQFP](/photos/12/31/123125/m30845fhgp_u3_sml.jpg)
M30845FHGP#U3
Manufacturer Part Number
M30845FHGP#U3
Description
IC M32C MCU FLASH 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Specifications of M30845FHGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Manufacturer
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M
R
R
e
E
3
. v
J
2
Table 11.2 Relocatable Vector Tables (Continued)
0
NOTES:
C
Bus Conflict Detect, Start Condition Detect, +156 to +159 (009C
Stop Condition Detect (UART2)
Bus Conflict Detect, Start Condition Detect, +160 to +163 (00A0
Stop Condition Detect (UART3/UART0)
Bus Conflict Detect, Start Condition Select, +164 to +167 (00A4
Stop Condition Detect(UART4/UART1)
A/D0
Key Input
Intelligent I/O Interrupt 0
Intelligent I/O Interrupt 1
Intelligent I/O Interrupt 2
Intelligent I/O Interrupt 3
Intelligent I/O Interrupt 4
Reserved Space
Intelligent I/O Interrupt 8
Intelligent I/O Interrupt 9, CAN 0
Intelligent I/O Interrupt 10, CAN 1
Reserved Space
CAN 2
Reserved Space
INT Instruction
1
9
0 .
8 /
B
1. These addresses are relative to those in the INTB register.
2. The I flag does not disable interrupts.
3. In I
4. The IFSR6 bit in the IFSR register determines whether these addresses are used for an interrupt in UART0 or in
0
1
4
0
The IFSR7 bit in the IFSR register determines whether these addresses are used for an interrupt in UART1 or in
UART3.
UART4.
3
G
J
6
u
o r
2
0 -
. l
C mode, NACK, ACK or start/stop condition detection causes interrupts to be generated.
u
0
1
Interrupt Generated by
p
, 7
0
1
(
2
M
(2)
0
0
3
5
2
C
8 /
Page 113
, 4
M
3
2
C
(3)
f o
8 /
4
4
) T
9
5
(4)
(4)
+168 to +171 (00A8
+172 to +175 (00AC
+176 to +179 (00B0
+180 to +183 (00B4
+184 to +187 (00B8
+188 to +191 (00BC
+192 to +195 (00C0
+196 to +207 (00C4
+208 to +211 (00D0
+212 to +215 (00D4
+216 to +219 (00D8
+220 to +227 (00DC
+228 to +231 (00E4
+232 to +255 (00E8
+0 to +3 (0000
+252 to +255 (00FC
Address("L") to Address("H")
Vector Table Address
16
to 0003
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
to 00B7
to 00A3
to 00A7
to 00AB
to 00B3
to 00BB
to 00E7
to 00FF
to 009F
to 00C3
to 00CF
to 00D3
to 00D7
to 00DB
to 00BF
to 00FF
to 00AF
to 00E3
16
) to
(1)
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
) 45
) 39
) 40
) 41
) 44
) 57
) 58 to 63
)
) 42
) 46
) 48
) 52
) 53
) 43
) 47
) 49 to 51
) 54
) 55, 56
0 to 63
Interrupt Number
Software
Serial I/O
A/D Converter
Interrupts
Intelligent I/O
Intelligent I/O
Intelligent I/O
CAN
CAN
Interrupts
Reference
11. Interrupts
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