ATTINY5-MAHR Atmel, ATTINY5-MAHR Datasheet - Page 6
![IC MCU AVR 512B FLASH 8UDFN](/photos/12/32/123206/8-udfn-8ma4_sml.jpg)
ATTINY5-MAHR
Manufacturer Part Number
ATTINY5-MAHR
Description
IC MCU AVR 512B FLASH 8UDFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY9-MAHR.pdf
(169 pages)
Specifications of ATTINY5-MAHR
Package / Case
8-UDFN Exposed Pad
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
512B (512 x 8)
Data Converters
A/D 4x8b
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
- Current page: 6 of 169
- Download datasheet (5Mb)
4. CPU Core
4.1
6
Architectural Overview
ATtiny4/5/9/10
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Figure 4-1.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 16 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Control Lines
Instruction
Instruction
Program
Memory
Reg ister
Decoder
Flash
Block Diagram of the AVR Architecture
Program
Counter
and Con trol
Reg istrers
I/O Lines
Purpose
General
SRA M
Data Bus 8-bit
Status
16 x 8
Data
ALU
Timer/Counter 0
Comparator
Watchdog
Interrupt
Timer
Analog
Unit
ADC
8127D–AVR–02/10
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