PIC10F204-I/P Microchip Technology, PIC10F204-I/P Datasheet - Page 28
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PIC10F204-I/P
Manufacturer Part Number
PIC10F204-I/P
Description
IC PIC MCU FLASH 256X12 8DIP
Manufacturer
Microchip Technology
Series
PIC® 10Fr
Datasheets
1.PIC10F200T-IOT.pdf
(96 pages)
2.PIC10F200T-IOT.pdf
(6 pages)
3.PIC10F200T-IOT.pdf
(18 pages)
4.PIC10F202-EP.pdf
(88 pages)
Specifications of PIC10F204-I/P
Program Memory Type
FLASH
Program Memory Size
384B (256 x 12)
Package / Case
8-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
3
Ram Size
16 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC10F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
16 B
Interface Type
USB
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC103003 - BOARD DEMO PIC10F CAP TOUCHAC162059 - HEADER INTRFC MPLAB ICD2 8/14PINAC164037 - MODULE SKT 6L PROMATE II SOT23
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC10F204-I/P
Manufacturer:
MICROCHIP
Quantity:
336
Part Number:
PIC10F204-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC10F200/202/204/206
TABLE 5-2:
5.4
5.4.1
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute the
bit operation and rewrite the result. Caution must be
used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit 2 of GPIO will cause
all eight bits of GPIO to be read into the CPU, bit 2 to
be set and the GPIO value to be written to the output
latches. If another bit of GPIO is used as a bidirectional
I/O pin (say bit 0) and it is defined as an input at this
time, the input signal present on the pin itself would be
read into the CPU and rewritten to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the Input mode, no problem occurs.
However, if bit 0 is switched into Output mode later on,
the content of the data latch may now be unknown.
Example 5-1 shows the effect of two sequential
Read-Modify-Write instructions (e.g., BCF, BSF, etc.)
on an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired OR”, “wired
AND”). The resulting high output currents may damage
the chip.
DS41239A-page 26
Address
N/A
N/A
03h
06h
Legend:
Note 1:
2:
I/O Programming Considerations
TRISGPIO
OPTION
STATUS
GPIO
Shaded cells are not used by Port registers, read as ‘0’, — = unimplemented, read as ‘0’, x = unknown, u = unchanged,
q = depends on condition.
If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
If Reset was due to wake-up on comparator change, then bit 6 = 1. All other Resets will cause bit 6 = 0.
BIDIRECTIONAL I/O PORTS
Name
SUMMARY OF PORT REGISTERS
GPWUF
GPWU
Bit 7
—
—
CWUF
GPPU
Bit 6
—
—
T0CS
Bit 5
—
—
—
Preliminary
T0SE
Bit 4
TO
—
—
I/O Control Register
Bit 3
PSA
GP3
PD
EXAMPLE 5-1:
5.4.2
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 5-2).
Therefore, care must be exercised if a write followed by
a read operation is carried out on the same I/O port. The
sequence of instructions should allow the pin voltage to
stabilize (load dependent) before the next instruction
causes that file to be read into the CPU. Otherwise, the
previous state of that pin may be read into the CPU rather
than the new state. When in doubt, it is better to separate
these instructions with a NOP or another instruction not
accessing this I/O port.
;Initial GPIO Settings
;GPIO<3:2> Inputs
;GPIO<1:0> Outputs
;
;
;
;
Note 1:
BCF
BCF
MOVLW
TRIS
Bit 2
GP2
PS2
Z
GPIO,
GPIO,
007h;
GPIO
Bit 1
GP1
SUCCESSIVE OPERATIONS ON
I/O PORTS
PS1
DC
The user may have expected the pin values
to be ---- pp00. The 2nd BCF caused GP1
to be latched as the pin value (High).
Bit 0
GP0
PS0
1 ;---- pp01
0 ;---- pp10
C
;---- pp10
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
GPIO latch
----------
2004 Microchip Technology Inc.
---- 1111
1111 1111
00-1 1xxx
---- xxxx
Power-On
Value on
Reset
GPIO pins
----------
---- pp11
---- pp11
---- pp11
All Other Resets
qq-q quuu
---- 1111
1111 1111
---- uuuu
Value on
(1, 2)