PIC16F505-E/ST Microchip Technology, PIC16F505-E/ST Datasheet - Page 16

• Manufacturer Part Number: PIC16F505-E/ST
• Description: IC MCU FLASH 1KX12 14TSSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F505-E/ST

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 11
• Program Memory Size: 1.5KB (1K x 12)
• Program Memory Type: FLASH
• Ram Size: 72 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 14-TSSOP
• For Use With: AC162070 - HEADER INTRFC MPLAB ICD2 8/14P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

PIC12F508/509/16F505
3.1
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC
is incremented every Q1 and the instruction is fetched
from program memory and latched into the instruction
register in Q4. It is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-3 and Example 3-1.
FIGURE 3-3:
EXAMPLE 3-1:
DS41236E-page 16
1. MOVLW 03H
2. MOVWF PORTB
3. CALL
4. BSF
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
Clocking Scheme/Instruction
Cycle
SUB_1
PORTB, BIT1
OSC1
PC
Q1
Q2
Q3
Q4
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC – 1)
Fetch INST (PC)
Q2
Fetch 1
PC
Q3
Execute 1
Q4
Fetch 2
Q1
Execute INST (PC)
Fetch INST (PC + 1)
Execute 2
Q2
Fetch 3
PC + 1
3.2
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g., GOTO), then two cycles
are required to complete the instruction (Example 3-1).
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q3
Execute 3
Q4
Fetch 4
Instruction Flow/Pipelining
Q1
Fetch SUB_1 Execute SUB_1
Execute INST (PC + 1)
Fetch INST (PC + 2)
Q2
Flush
© 2009 Microchip Technology Inc.
PC + 2
Q3
Q4
Internal
phase
clock