ATTINY5-TS8R Atmel, ATTINY5-TS8R Datasheet - Page 104

• Manufacturer Part Number: ATTINY5-TS8R
• Description: IC MCU AVR 512B FLASH SOT-23-6
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY5-TS8R

• Package / Case: SOT-23-6
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 12MHz
• Number Of I /o: 4
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Program Memory Size: 512B (512 x 8)
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Peripherals: POR, PWM, WDT
• Core Size: 8-Bit
• Processor Series: ATTINY5x
• Core: AVR8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

14.5.2
14.5.3
14.5.4
14.5.5
104
ATtiny4/5/9/10
SST - Serial STore to data space using indirect addressing
SSTPR - Serial STore to Pointer Register
SIN - Serial IN from i/o space using direct addressing
SOUT - Serial OUT to i/o space using direct addressing
The SST instruction uses indirect addressing to store into data space the byte that is shifted into
the physical layer shift register. The data space location is pointed by the Pointer Register (PR),
where the address must have been stored before the operation. The Pointer Register can be
either left unchanged by the operation, or it can be post-incremented, as shown in
Table 14-3.
The SSTPR instruction stores the data byte that is shifted into the physical layer shift register to
the Pointer Register (PR). The address bit of the instruction specifies which byte of the Pointer
Register is accessed, as shown in
Table 14-4.
The SIN instruction loads data byte from the I/O space to the shift register of the physical layer
for serial read-out. The instuction uses direct addressing, the address consisting of the 6
address bits of the instruction, as shown in
Table 14-5.
The SOUT instruction stores the data byte that is shifted into the physical layer shift register to
the I/O space. The instruction uses direct addressing, the address consisting of the 6 address
bits of the instruction, as shown in
Table 14-6.
Operation
DS[PR]
DS[PR]
Operation
PR[a]
Operation
data
Operation
I/O[a]
←
←
←
←
←
I/O[a]
data
data
data
data
The Serial Store to Data Space (SLD) Instruction
The Serial Store to Pointer Register (SSTPR) Instruction
The Serial IN from i/o space (SIN) Instruction
The Serial OUT to i/o space (SOUT) Instruction
Opcode
0110 0000
0110 0100
Opcode
0110 100a
Opcode
0aa1 aaaa
Opcode
1aa1 aaaa
Table
Table
14-6.
14-4.
Table
Remarks
PR
PR
Remarks
Bit ‘a’ addresses Pointer Register byte
Remarks
Bits marked ‘a’ form the direct, 6-bit addres
Remarks
Bits marked ‘a’ form the direct, 6-bit addres
14-5.
←
←
PR
PR + 1
Register
Unchanged
Post increment
8127D–AVR–02/10
Table
14-3.