ATTINY10-TS8R Atmel, ATTINY10-TS8R Datasheet - Page 44
ATTINY10-TS8R
Manufacturer Part Number
ATTINY10-TS8R
Description
IC MCU AVR 1K FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY9-MAHR.pdf
(169 pages)
Specifications of ATTINY10-TS8R
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
1KB (1K x 8)
Data Converters
A/D 4x8b
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY10-TS8R
Manufacturer:
NUVOTON
Quantity:
43
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10.2.4
44
ATtiny4/5/9/10
Reading the Pin Value
Figure 10-3. Switching Between Input and Output in Break-Before-Make-Mode
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
ing latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay.
shows a timing diagram of the synchronization when reading an externally applied pin value.
The maximum and minimum propagation delays are denoted t
Figure 10-4. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
INSTRUCTIONS
SYSTEM CLK
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
PORTx
DDRx
Px0
Px1
r16
r17
PINxn
r17
0x01
tri-state
out DDRx, r16
Figure 10-2 on page
XXX
intermediate tri-state cycle
0x02
tri-state
nop
t
pd, max
0x02
0x01
0x55
0x00
XXX
42, the PINxn Register bit and the preced-
out DDRx, r17
t
pd, min
pd,max
in r17, PINx
and t
intermediate tri-state cycle
tri-state
0x01
pd,min
respectively.
8127D–AVR–02/10
0xFF
Figure 10-4
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