ATTINY20-XUR Atmel, ATTINY20-XUR Datasheet - Page 73

• Manufacturer Part Number: ATTINY20-XUR
• Description: MCU AVR 2KB FLASH 12MHZ 14TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY20-XUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8235B–AVR–04/11
Table 11-6
Table 11-6.
Note:
Table 11-7
correct PWM mode.
Table 11-7.
Note:
• Bits 3:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 1:0 – WGM0[1:0] : Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see
COM0B1
COM0B1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
shows COM0B[1:0] bit functionality when WGM0[2:0] bits are set to fast PWM mode.
pare Match is ignored, but the set or clear is done at BOTTOM. See
page 66
pare Match is ignored, but the set or clear is done at TOP. See
page 68
shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to phase
Compare Output Mode, Fast PWM Mode
Compare Output Mode, Phase Correct PWM Mode
COM0B0
COM0B0
for more details.
for more details.
0
1
0
1
0
1
0
1
Description
Normal port operation, OC0B disconnected.
Reserved
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
Description
Normal port operation, OC0B disconnected.
Reserved
Clear OC0B on Compare Match, set OC0B at BOTTOM
(non-inverting mode)
Set OC0B on Compare Match, clear OC0B at BOTTOM
(inverting mode)
Table
11-8. Modes of operation supported by the Timer/Counter
“Modes of Operation” on page
(1)
(1)
“Phase Correct PWM Mode” on
“Fast PWM Mode” on
65).
ATtiny20
73