ATTINY13A-MUR Atmel, ATTINY13A-MUR Datasheet - Page 39
![MCU AVR 1KB FLASH 20MHZ 20QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY13A-MUR
Manufacturer Part Number
ATTINY13A-MUR
Description
MCU AVR 1KB FLASH 20MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY13A-SSH.pdf
(176 pages)
Specifications of ATTINY13A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (5Mb)
8126E–AVR–07/10
value is reached. If the system doesn't restart the counter, an interrupt or system reset will be
issued.
Figure 8-7.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used
to wake the device from sleep-modes, and also as a general system timer. One example is to
limit the maximum time allowed for certain operations, giving an interrupt when the operation
has run longer than expected. In System Reset mode, the WDT gives a reset when the timer
expires. This is typically used to prevent system hang-up in case of runaway code. The third
mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-
rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown
by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to Sys-
tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt
mode bit (WDTIE) are locked to 1 and 0 respectively. To further ensure program security, altera-
tions to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and
changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE)
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as
and WDE. A logic one must be written to WDE regardless of the previous value of the
WDE bit.
desired, but with the WDCE bit cleared. This must be done in one operation.
WATCHDOG
RESET
OSCILLATOR
Watchdog Timer
128kHz
WDTIE
WDTIF
WDE
WDP0
WDP1
WDP2
WDP3
MCU RESET
INTERRUPT
39
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