ATTINY24A-CCUR Atmel, ATTINY24A-CCUR Datasheet - Page 16
ATTINY24A-CCUR
Manufacturer Part Number
ATTINY24A-CCUR
Description
MCU AVR 2KB FLASH 20MHZ 15UFBGA
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY24A-MU.pdf
(286 pages)
Specifications of ATTINY24A-CCUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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5.2.1
5.3
16
EEPROM Data Memory
ATtiny24A/44A/84A
Data Memory Access Times
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter-
nal data SRAM in the ATtiny24A/44A/84A are all accessible through all these addressing
modes. The Register File is described in
Figure 5-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 5-3.
The ATtiny24A/44A/84A contains 128/256/512 bytes of data EEPROM memory. It is organized
as a separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register. For a detailed description of Serial data
downloading to the EEPROM, see
Address
clk
Data
Data
Data Memory Map
On-chip Data SRAM Access Cycles
WR
CPU
RD
(128/256/512 x 8)
64 I/O Registers
Compute Address
Data Memory
Internal SRAM
32 Registers
T1
Memory Access Instruction
“Serial Programming” on page
“General Purpose Register File” on page
0x0DF/0x015F/0x025F
0x0000 - 0x001F
0x0020 - 0x005F
0x0060
Address valid
CPU
T2
cycles as illustrated in
Next Instruction
162.
T3
Figure
8183C–AVR–03/11
9.
5-3.
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