ATTINY13A-SN Atmel, ATTINY13A-SN Datasheet - Page 106
![IC MCU AVR 1KB FLASH 20MHZ 8SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY13A-SN
Manufacturer Part Number
ATTINY13A-SN
Description
IC MCU AVR 1KB FLASH 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY13A-SSH.pdf
(176 pages)
Specifications of ATTINY13A-SN
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Processor Series
ATTINY1x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAKSTK511
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY13A-SN
Manufacturer:
MICROCHIP
Quantity:
3 000
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17.6
106
Serial Programming
ATtiny13A
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). See
Figure 17-1. Serial Programming and Verify
Note:
After RESET is set low, the Programming Enable instruction needs to be executed first before
program/erase operations can be executed.
Table 17-7.
Note:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
If clocked by internal oscillator there is no need to connect a clock source to the CLKI pin.
In
dedicated for the internal SPI interface.
Symbol
MOSI
MISO
Figure
SCK
Table 17-7
RESET
Pin Mapping Serial Programming
17-1.
above, the pin mapping for SPI programming is listed. Not all parts use the SPI pins
ck
ck
Pins
PB0
PB1
PB2
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
PB5
GND
VCC
PB2
PB1
PB0
I/O
O
I
I
+1.8 - 5.5V
ck
ck
>= 12 MHz
>= 12 MHz
Description
Serial Data in
Serial Data out
Serial Clock
SCK
MISO
MOSI
8126E–AVR–07/10
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