ATTINY13A-SS7 Atmel, ATTINY13A-SS7 Datasheet - Page 70
![IC MCU AVR 1K FLASH 8SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY13A-SS7
Manufacturer Part Number
ATTINY13A-SS7
Description
IC MCU AVR 1K FLASH 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY13A-SSH.pdf
(176 pages)
Specifications of ATTINY13A-SS7
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 105 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY13A-SS7R
Manufacturer:
Atmel
Quantity:
8 052
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11.9
11.9.1
70
Register Description
ATtiny13A
TCCR0A – Timer/Counter Control Register A
Figure 11-11
PWM mode where OCR0A is TOP.
Figure 11-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
• Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A[1:0]
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A[1:0] bits depends on the
WGM0[2:0] bit setting.
Table 11-2
or CTC mode (non-PWM).
Table 11-2.
TCNTn
(clk
(CTC)
OCRnx
OCFnx
Bit
0x2F
Read/Write
Initial Value
clk
clk
COM0A1
I/O
I/O
Tn
/8)
0
0
1
1
shows the COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to a normal
shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast
caler (f
COM0A1
Compare Output Mode, non-PWM Mode
R/W
COM0A0
7
0
0
1
0
1
clk_I/O
TOP - 1
COM0A0
R/W
/8)
6
0
Description
Normal port operation, OC0A disconnected.
Toggle OC0A on Compare Match
Clear OC0A on Compare Match
Set OC0A on Compare Match
COM0B1
R/W
5
0
COM0B0
R/W
TOP
4
0
TOP
R
3
–
0
R
2
–
0
BOTTOM
WGM01
R/W
1
0
WGM00
R/W
0
0
BOTTOM + 1
8126E–AVR–07/10
TCCR0A
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